| Detailed routing by sparse grid graph and minimum-area-captured path search G Chen, CW Pui, H Li, J Chen, B Jiang, EFY Young Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 70* | 2019 |
| Dr. CU 2.0: A scalable detailed routing framework with correct-by-construction design rule satisfaction H Li, G Chen, B Jiang, J Chen, EFY Young 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019 | 62 | 2019 |
| Neural-ILT: Migrating ILT to neural networks for mask printability and complexity co-optimization B Jiang, L Liu, Y Ma, H Zhang, B Yu, EFY Young Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 45 | 2020 |
| A fast machine learning-based mask printability predictor for OPC acceleration B Jiang, H Zhang, J Yang, EFY Young Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 35 | 2019 |
| Neural-ILT 2.0: Migrating ilt to domain-specific and multitask-enabled neural network B Jiang, L Liu, Y Ma, B Yu, EFY Young IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 25 | 2021 |
| A2-ILT: GPU accelerated ILT with spatial attention mechanism Q Wang, B Jiang, MDF Wong, EFY Young Proceedings of the 59th ACM/IEEE Design Automation Conference, 967-972, 2022 | 18 | 2022 |
| Fit: Fill insertion considering timing B Jiang, X Zhang, R Chen, G Chen, P Tu, W Li, EFY Young, B Yu Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 15 | 2019 |
| CU. POKer: Placing DNNs on wafer-scale AI accelerator with optimal kernel sizing B Jiang, J Chen, J Liu, L Liu, F Wang, X Zhang, EFY Young Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 12 | 2020 |
| Building up end-to-end mask optimization framework with self-training B Jiang, X Zhang, L Liu, EFY Young Proceedings of the 2021 International Symposium on Physical Design, 63-70, 2021 | 9 | 2021 |
| Machine-learning based clustering for clock tree synthesis B Jiang, N Viswanathan, Z Li, YX Ding US Patent 11,645,441, 2023 | 4 | 2023 |
| Exploring rule-free layout decomposition via deep reinforcement learning B Jiang, X Zang, MDF Wong, EFY Young IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 2 | 2022 |
| Size-Optimized Depth-Constrained Large Parallel Prefix Circuits S Lin, B Jiang, W Sheng, E Young Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 1 | 2024 |
| Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology L Liu, T Liu, B Jiang, EFY Young IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| Partition and place finite element model on wafer-scale engine J Liu, X Zhang, S Lin, X Zang, J Chen, B Jiang, MDF Wong, EFY Young Proceedings of the 59th ACM/IEEE Design Automation Conference, 631-636, 2022 | 1 | 2022 |
| Dynamic weighting scheme for local cluster refinement B Jiang, N Viswanathan, WR Reece, Z Li US Patent 11,188,702, 2021 | 1 | 2021 |
| CU. POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization B Jiang, J Chen, J Liu, L Liu, F Wang, X Zhang, EFY Young IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 1 | 2021 |
| Machine-learning based prediction method for iterative clustering during clock tree synthesis B Jiang, N Viswanathan, Z Li, YX Ding US Patent 11,244,099, 2022 | | 2022 |
| Towards Automated End-to-End VLSI Design for Manufacturability Solutions B Jiang PQDT-Global, 2021 | | 2021 |
