Shaizeen Aga
Shaizeen Aga
AMD Research
Verified email at amd.com - Homepage
Title
Cited by
Cited by
Year
Compute caches
S Aga, S Jeloka, A Subramaniyan, S Narayanasamy, D Blaauw, R Das
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
1742017
Invisimem: Smart memory defenses for memory bus side channel
S Aga, S Narayanasamy
ACM SIGARCH Computer Architecture News 45 (2), 94-106, 2017
482017
Efficiently enforcing strong memory ordering in GPUs
A Singh, S Aga, S Narayanasamy
Proceedings of the 48th International Symposium on Microarchitecture, 699-712, 2015
172015
MOCA: Memory object classification and allocation in heterogeneous memory systems
A Narayan, T Zhang, S Aga, S Narayanasamy, A Coskun
2018 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2018
142018
InvisiPage: Oblivious demand paging for secure enclaves
S Aga, S Narayanasamy
Proceedings of the 46th International Symposium on Computer Architecture …, 2019
102019
Co-ML: a case for Collaborative ML acceleration using near-data processing
S Aga, N Jayasena, M Ignatowski
Proceedings of the International Symposium on Memory Systems, 506-517, 2019
62019
InvisiMem: Smart Memory for Trusted Computing
S Aga, S Narayanasamy
International Symposium on Computer Architecture 10 (3079856.3080232), 2017
52017
SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks
S Pati, S Aga, MD Sinclair, N Jayasena
2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020
42020
zfence: Data-less coherence for efficient fences
S Aga, A Singh, S Narayanasamy
Proceedings of the 29th ACM on International Conference on Supercomputing …, 2015
42015
Ordering constraint management within coherent memory systems
AGA Shaizeen, A Singh, S Narayanasamy
US Patent 9,367,461, 2016
32016
Cilkspec: optimistic concurrency for cilk
S Aga, S Krishnamoorthy, S Narayanasamy
SC'15: Proceedings of the International Conference for High Performance …, 2015
32015
Memory allocation for processing-in-memory operations
A Nag, N Jayasena, AGA Shaizeen
US Patent App. 16/828,190, 2021
2021
Lightweight memory ordering primitives
N Jayasena, AGA Shaizeen, A Nag
US Patent App. 16/808,346, 2021
2021
Near-memory data reduction
N Jayasena, AGA Shaizeen
US Patent 11,099,788, 2021
2021
Device and method for accelerating matrix multiply operations
AGA Shaizeen, N Jayasena, AH Rush, M Ignatowski
US Patent App. 17/208,526, 2021
2021
Demystifying BERT: Implications for Accelerator Design
S Pati, S Aga, N Jayasena, MD Sinclair
arXiv preprint arXiv:2104.08335, 2021
2021
Device and method for accelerating matrix multiply operations
AGA Shaizeen, N Jayasena, AH Rush, M Ignatowski
US Patent 10,956,536, 2021
2021
Device and method for accelerating matrix multiply operations as a sum of outer products
AGA Shaizeen, N Jayasena, AH Rush, M Ignatowski
US Patent 10,902,087, 2021
2021
Near-memory data-dependent gather and packing
AGA Shaizeen, N Jayasena
US Patent 10,782,918, 2020
2020
Trusted computing system with enhanced memory
S Narayanasamy, AGA Shaizeen
US Patent 10,496,552, 2019
2019
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