| Compiling HPC kernels for the REDEFINE CGRA KT Madhu, S Das, S Nalesh, SK Nandy, R Narayan 2015 IEEE 17th International Conference on High Performance Computing and …, 2015 | 21 | 2015 |
| A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths S Das, K Madhu, M Krishna, N Sivanandan, F Merchant, S Natarajan, ... Journal of Systems Architecture 60 (7), 592-614, 2014 | 21 | 2014 |
| Rhyme: Redefine hyper cell multicore for accelerating hpc kernels S Das, N Sivanandan, KT Madhu, SK Nandy, R Narayan 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 11 | 2016 |
| Synthesis of instruction extensions on hypercell, a reconfigurable datapath KT Madhu, S Das, CM Krishna, S Nalesh, SK Nandy, R Narayan 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 11 | 2014 |
| Energy aware synthesis of application kernels expressed in functional languages on a coarse grained composable reconfigurable array S Nalesh, KT Madhu, S Das, SK Nandy, R Narayan 2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015 | 4 | 2015 |
| Task allocation of safety-critical applications on reconfigurable multi-core architectures T Guillaumet, E Feron, P Baufreton, F Neumann, K Madhu, M Krishna, ... 2017 IEEE/AIAA 36th Digital Avionics Systems Conference (DASC), 1-10, 2017 | 2 | 2017 |
| Energy aware synthesis of application kernels through composition of data-paths on a CGRA S Nalesh, KT Madhu, S Das, SK Nandy, R Narayan Integration 58, 320-328, 2017 | 2 | 2017 |
| Autotuning LSTM for Accelerated Execution on Edge A Saluja, A Mitra, A Deshwal, K Madhu, U Chugh, S Lee, J Song 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 1 | 2021 |
| Flexible resource allocation and management for application graphs on renE mpsoc KT Madhu, A Rao, S Das, KC Madhava, SK Nandy, R Narayan Proceedings of the 7th Workshop on Parallel Programming and Run-Time …, 2016 | 1 | 2016 |
| Compiler controlled Task Management in Runtime Systems for Dynamic Data ow Model of Execution KT Madhu | | 2022 |
| Transport Triggered near Memory Accelerator for Deep Learning K Madhu, S Das, A Tyagi, A Deshwal, J Song, S Lee 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | | 2021 |
| Work-in-Progress: REDEFINE (R)(TM)-A Case for WCET-friendly Hardware Accelerators for Real time Applications K Madhu, T Singla, SK Nandy, R Narayan, F Neumann, P Baufreton IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2017 | | 2017 |
| Accelerating HPC Kernels with RHyMe-REDEFINE HyperCell Multicore S Das, S Nalesh, KT Madhu, SK Nandy, R Narayan | | |
Saptarsi DasSamsung SemiconductorVerified email at cadl.iisc.ernet.in
