Sajib Kumar Mitra
Sajib Kumar Mitra
Engineer at Bangladesh Bank
Verified email at bb.org.bd - Homepage
Title
Cited by
Cited by
Year
Minimum cost fault tolerant adder circuits in reversible logic synthesis
SK Mitra, AR Chowdhury
2012 25th International Conference on VLSI Design, 334-339, 2012
532012
Efficient approach to design low power reversible logic blocks for Field Programmable Gate Arrays
ASM Sayem, SK Mitra
Computer Science and Automation Engineering (CSAE), 2011 IEEE International …, 2011
142011
An efficient approach for designing and minimizing reversible programmable logic arrays
SK Mitra, L Jamal, M Kaneko, HM Hasan Babu
Proceedings of the great lakes symposium on VLSI, 215-220, 2012
132012
On the analysis of Reversible Booth's Multiplier
J Sultana, SK Mitra, AR Chowdhury
2015 28th International Conference on VLSI Design, 170-175, 2015
82015
Optimized logarithmic barrel shifter in reversible logic synthesis
SK Mitra, AR Chowdhury
2015 28th International Conference on VLSI Design, 441-446, 2015
62015
Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis
AR Chowdhury, SK Mitra
22012
Efficient Approach to design Reversible FaultTolerant Cyclic Redundancy Check Circuit
SK Mitra, T Sultana, S Anwar, AR Chowdhury
Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011
12011
Reversible Programmable Logic Arrays
SK Mitra, MR Rahman
2016 29th International Conference on VLSI Design and 2016 15th …, 2016
2016
Efficient Design of Check Circuit to detect MultipleCell Errors in Reversible Logic Synthesis
SK Mitra, AR Anwar, Shahed, Chowdhury
Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011
2011
Online Testable Fault Tolerant Full Adder in Reversible Logic Synthesis
SK Mitra, MF Hossain, S Anwar, AR Chowdhury
Second International Conference on Signals, Systems & Automation (ICSSA-11 …, 2011
2011
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Articles 1–10