| Spin-based computing: Device concepts, current status, and a case study on a high-performance microprocessor J Kim, A Paul, PA Crowell, SJ Koester, SS Sapatnekar, JP Wang, CH Kim Proceedings of the IEEE 103 (1), 106-130, 2014 | 184 | 2014 |
| Distributed On-Chip Switched-Capacitor DC--DC Converters Supporting DVFS in Multicore Systems P Zhou, A Paul, CH Kim, SS Sapatnekar IEEE, 2013 | 24 | 2013 |
| Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities A Paul, D Jiao, S Sapatnekar, CH Kim 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 49-52, 2013 | 18 | 2013 |
| A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI P Jain, A Paul, X Wang, CH Kim 2012 International Electron Devices Meeting, 9.7. 1-9.7. 4, 2012 | 15 | 2012 |
| Fast characterization of PBTI and NBTI induced frequency shifts under a realistic recovery bias using a ring oscillator based circuit X Wang, S Song, A Paul, CH Kim 2014 IEEE International Reliability Physics Symposium, 6B. 2.1-6B. 2.6, 2014 | 13 | 2014 |
| System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators A Paul, SP Park, D Somasekhar, YM Kim, N Borkar, UR Karpuzcu, ... IEEE, 2016 | 10 | 2016 |
| Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors A Paul, M Amrein, S Gupta, A Vinod, A Arun, S Sapatnekar, CH Kim Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 8 | 2012 |
| Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors A Paul, M Amrein, S Gupta, A Vinod, A Arun, S Sapatnekar, CH Kim SRC TECHCON 2012, 2012 | 8 | 2012 |
| A modular system for capacitive ECG-acquisition HG Despang, A Weder, M Pietzsch, O Lindner, A Heinig, W Rentsch, ... Biomedical Engineering/Biomedizinische Technik 58 (SI-1-Track-I …, 2013 | 2 | 2013 |
| Circuit Design and Modeling Techniques of On-chip Power Delivery Modules A Paul University of Minnesota, Twin Cities, USA, 2017 | | 2017 |
| Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold Variations A Paul, C Kshirsagar, SS Sapatnekar, S Koester, CH Kim 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | | 2014 |
| Staggered Core Activation: Staggered Core Activation: A Circuit/Architectural Approach for Mitigating Resonant Supply Noise Mitigating Resonant Supply Noise Issues in Multi … A Paul, MASGA Vinod, M Amrein, S Gupta, A Vinod, A Arun, S Sapatnekar, ... | | |
Jongyeon KimUniversity of minnesota, Yonsei universityVerified email at umn.edu
