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Alireza Mahzoon
Alireza Mahzoon
Verified email at informatik.uni-bremen.de - Homepage
Title
Cited by
Cited by
Year
RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers
A Mahzoon, D Große, R Drechsler
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
632019
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers
A Mahzoon, D Große, R Drechsler
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
552018
Towards formal verification of optimized and industrial multipliers
A Mahzoon, D Große, C Scholl, R Drechsler
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 544-549, 2020
412020
Late breaking results: Polynomial formal verification of fast adders
A Mahzoon, R Drechsler
2021 58th ACM/IEEE Design Automation Conference (DAC), 1376-1377, 2021
272021
Polynomial formal verification of prefix adders
A Mahzoon, R Drechsler
2021 IEEE 30th Asian Test Symposium (ATS), 85-90, 2021
262021
RevSCA-2.0: SCA-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal
A Mahzoon, D Große, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
252021
Polynomial word-level verification of arithmetic circuits
M Barhoush, A Mahzoon, R Drechsler
Proceedings of the 19th ACM-IEEE International Conference on Formal Methods …, 2021
202021
Polynomial formal verification: Ensuring correctness under resource constraints
R Drechsler, A Mahzoon
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022
182022
Combining symbolic computer algebra and boolean satisfiability for automatic debugging and fixing of complex multipliers
A Mahzoon, D Große, R Drechsler
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 351-356, 2018
182018
Polynomial formal verification of arithmetic circuits
R Drechsler, A Mahzoon, L Weingarten
Proceedings of International Conference on Computational Intelligence and …, 2022
152022
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
A Mahzoon, D Große, R Drechsler
Recent Findings in Boolean Techniques: Selected Papers from the 14th …, 2021
152021
Verifying dividers using symbolic computer algebra and don't care optimization
C Scholl, A Konrad, A Mahzoon, D Große, R Drechsler
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
122021
Towards polynomial formal verification of complex arithmetic circuits
R Drechsler, A Mahzoon, M Goli
2022 25th International Symposium on Design and Diagnostics of Electronic …, 2022
112022
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability
A Mahzoon, D Große, C Scholl, A Konrad, R Drechsler
Proceedings of the 59th ACM/IEEE Design Automation Conference, 1183-1188, 2022
102022
Multiplier Generator GenMul
A Mahzoon, D Große, R Drechsler
72019
Polynomial formal verification of floating point adders
J Kleinekathöfer, A Mahzoon, R Drechsler
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-2, 2023
62023
OptiFEX: A framework for exploring area-efficient floating point expressions on FPGAs with optimized exponent/mantissa widths
A Mahzoon, B Alizadeh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 198-209, 2016
62016
Towards polynomial formal verification of AI-generated arithmetic circuits
R Drechsler, A Mahzoon
2023 International Symposium on Devices, Circuits and Systems (ISDCS) 1, 01-04, 2023
42023
ASCHyRO: Automatic fault localization of SystemC HLS designs using a hybrid accurate rank ordering technique
M Goli, A Mahzoon, R Drechsler
2020 IEEE 38th International Conference on Computer Design (ICCD), 179-186, 2020
42020
Multi-objective optimization of floating point arithmetic expressions using iterative factorization
A Mahzoon, B Alizadeh
2015 IEEE Computer Society Annual Symposium on VLSI, 243-248, 2015
42015
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