David Z. Pan
David Z. Pan
Silicon Labs Endowed Chair Professor, ECE, University of Texas at Austin
Verified email at ece.utexas.edu - Homepage
Title
Cited by
Cited by
Year
Interconnect design for deep submicron ICs
Z Pan, L He, CK Koh, KY Khoo
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
2441997
Pushing ASIC performance in a power envelope
R Puri, L Stok, J Cohn, D Kung, D Pan, D Sylvester, A Srivastava, ...
Proceedings of the 40th annual Design Automation Conference, 788-793, 2003
2032003
Redundant-via enhanced maze routing for yield improvement
G Xu, LD Huang, DZ Pan, MDF Wong
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
1832005
Improved crosstalk modeling for noise constrained interconnect optimization
J Cong, DZ Pan, PV Srinivas
Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001
1792001
Buffer block planning for interconnect-driven floorplanning
J Cong, T Kong, DZ Pan
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
1791999
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits
S Bobba, A Chakraborty, O Thomas, P Batude, T Ernst, O Faynot, DZ Pan, ...
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 336-343, 2011
1782011
AppSAT: Approximately deobfuscating integrated circuits
K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin
2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017
1672017
Layout decomposition for triple patterning lithography
B Yu, K Yuan, D Ding, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
1622015
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
M Jung, J Mitra, DZ Pan, SK Lim
Communications of the ACM 57 (1), 107-115, 2014
1502014
Double patterning layout decomposition for simultaneous conflict and stitch minimization
K Yuan, JS Yang, DZ Pan
IEEE transactions on computer-aided design of integrated circuits and …, 2010
1472010
RADAR: RET-aware detailed routing using fast lithography simulations
J Mitra, P Yu, DZ Pan
Proceedings of the 42nd annual Design Automation Conference, 369-372, 2005
1392005
TSV stress aware timing analysis with applications to 3D-IC layout optimization
JS Yang, K Athikulwongse, YJ Lee, SK Lim, DZ Pan
Design Automation Conference, 803-806, 2010
1382010
A high-performance droplet routing algorithm for digital microfluidic biochips
M Cho, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
1372008
BoxRouter: a new global router based on box expansion and progressive ILP
M Cho, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007
1372007
BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router
M Cho, K Lu, K Yuan, DZ Pan
2007 IEEE/ACM International Conference on Computer-Aided Design, 503-508, 2007
1282007
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
K Athikulwongse, A Chakraborty, JS Yang, DZ Pan, SK Lim
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 669-674, 2010
1152010
Provably secure camouflaging strategy for IC protection
M Li, K Shamsi, T Meade, Z Zhao, B Yu, Y Jin, DZ Pan
IEEE transactions on computer-aided design of integrated circuits and systems, 2017
1072017
TACO: temperature aware clock-tree optimization
M Cho, S Ahmedtt, DZ Pan
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
992005
Cyclic obfuscation for creating SAT-unresolvable circuits
K Shamsi, M Li, T Meade, Z Zhao, DZ Pan, Y Jin
Proceedings of the on Great Lakes Symposium on VLSI 2017, 173-178, 2017
932017
Design for manufacturing with emerging nanolithography
DZ Pan, B Yu, JR Gao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
912013
The system can't perform the operation now. Try again later.
Articles 1–20