SRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks J Mu, H Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2412-2422, 2022 | 17 | 2022 |
A scalable cmos ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems Y Su, J Mu, H Kim, B Kim IEEE Journal of Solid-State Circuits 57 (3), 858-868, 2022 | 17 | 2022 |
A 1-16b reconfigurable 80kb 7t sram-based digital near-memory computing macro for processing neural networks H Kim, J Mu, C Yu, TTH Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1580-1590, 2023 | 15 | 2023 |
29.2 A 21× 21 Dynamic-Precision Bit-Serial Computing Graph Accelerator for Solving Partial Differential Equations Using Finite Difference Method J Mu, B Kim 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 406-408, 2021 | 11 | 2021 |
A 20x28 spins hybrid in-memory annealing computer featuring voltage-mode analog spin operator for solving combinatorial optimization problems J Mu, Y Su, B Kim 2021 Symposium on VLSI Technology, 1-2, 2021 | 9 | 2021 |
A dynamic-precision bit-serial computing hardware accelerator for solving partial differential equations using finite difference method J Mu, B Kim IEEE Journal of Solid-State Circuits 58 (2), 543-553, 2022 | 6 | 2022 |
BP-SCIM: A reconfigurable 8T SRAM macro for bit-parallel searching and computing in-memory Y Chen, J Mu, H Kim, L Lu, TTH Kim IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 5 | 2023 |
A scalable bit-serial computing hardware accelerator for solving 2D/3D partial differential equations using finite difference method J Mu, C Yu, TTH Kim, B Kim ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 5 | 2022 |
A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory Y Chen, J Mu, H Kim, L Lu, TTH Kim 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2556-2560, 2022 | 3 | 2022 |
A 252 spins scalable CMOS Ising chip featuring sparse and reconfigurable spin interconnects for combinatorial optimization problems Y Su, J Mu, H Kim, B Kim 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 3 | 2021 |
A 65nm logic-compatible embedded and flash memory for in-memory computation of artificial neural networks J Mu, B Kim 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2020 | 3 | 2020 |
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing Q Zang, WL Goh, L Lu, C Yu, J Mu, TTH Kim, B Kim, D Lit, AT Dot 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | 2 | 2023 |
A Continuous-Time Ising Machine using Coupled Inverter Chains Featuring Fully-Parallel One-Shot Spin Updates C Yu, J Mu, K Chai, T Kim, B Kim 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 1 | 2023 |
A Time-Domain Wavefront Computing Accelerator With a 32 32 Reconfigurable PE Array C Yu, J Mu, Y Su, KTC Chai, TTH Kim, B Kim IEEE Journal of Solid-State Circuits, 2023 | 1 | 2023 |
A 1Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation J Mu, L Lu, JE Kim, B An, V Sharma, AJ Lekshmi, PA Dananjaya, WH Lai, ... IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations J Mu, C Yu, TTH Kim, B Kim IEEE Journal of Solid-State Circuits, 2024 | | 2024 |
A Bit-Serial Computing Accelerator for Solving Coupled Partial Differential Equations J Mu, C Yu, TTH Kim, B Kim 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | | 2023 |
A Graph-Based Accelerator of Retinex Model with Bit-Serial Computing for Image Processing Z Wei, J Mu, Z Lu, Y Zheng, TTH Kim, B Kim 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
Energy-efficient hardware accelerators based on bit-serial graph and memory-centric computing architectures J Mu Nanyang Technological University, 2023 | | 2023 |