| Leveraging reconfigurability to raise productivity in FPGA functional debug Z Poulos, YS Yang, J Anderson, A Veneris, B Le 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 292-295, 2012 | 16 | 2012 |
| Non-solution implications using reverse domination in a modern SAT-based debugging environment B Le, H Mangassarian, B Keng, A Veneris 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 629-634, 2012 | 13 | 2012 |
| Simulation and satisfiability guided counter-example triage for rtl design debugging Z Poulos, YS Yang, A Veneris, B Le Fifteenth International Symposium on Quality Electronic Design, 618-624, 2014 | 10 | 2014 |
| Debugging RTL using structural dominance H Mangassarian, B Le, A Veneris IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 10 | 2013 |
| Automated debugging of missing assumptions B Keng, E Qin, A Veneris, B Le 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 732-737, 2014 | 8 | 2014 |
| Reviving erroneous stability-based clock-gating using partial max-SAT B Le, D Sengupta, A Veneris 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 717-722, 2013 | 6 | 2013 |
| Leveraging dominators for preprocessing QBF H Mangassarian, B Le, A Goultiaeva, A Veneris, F Bacchus 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 5 | 2010 |
| Accelerating post silicon debug of deep electrical faults B Le, D Sengupta, A Veneris, Z Poulos 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 61-66, 2013 | 4 | 2013 |
| Constructing stability-based clock gating with hierarchical clustering B Le, D Maksimovic, D Sengupta, E Ergin, R Berryhill, A Veneris 2015 25th International Workshop on Power and Timing Modeling, Optimization …, 2015 | 2 | 2015 |
| Multiple clock domain synchronization in a QBF-based verification environment D Maksimovic, B Le, A Veneris 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 684-689, 2014 | 1 | 2014 |
| SAT-based Automated Design Debugging: Improvements and Application to Low-Power Design B Le University of Toronto (Canada), 2012 | | 2012 |
| Propelling SAT-based Debugging using Reverse Domination B Le, H Mangassarian, B Keng, A Veneris | | |
