| " I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data MU Haque, I Dharmadasa, ZT Sworna, RN Rajapakse, H Ahmad arXiv preprint arXiv:2212.05856, 2022 | 247 | 2022 |
| Apiro: A framework for automated security tools api recommendation ZT Sworna, C Islam, MA Babar ACM Transactions on Software Engineering and Methodology 32 (1), 1-42, 2023 | 19 | 2023 |
| An improved design of a reversible fault tolerant lut-based fpga MU Haque, ZT Sworna, HMH Babu 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 13 | 2016 |
| NLP methods in host-based intrusion detection Systems: A systematic review and future directions ZT Sworna, Z Mousavi, MA Babar Journal of Network and Computer Applications, 103761, 2023 | 11 | 2023 |
| Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array ZT Sworna, M UlHaque, N Tara, HM Hasan Babu, AK Biswas IET Circuits, Devices & Systems 10 (3), 163-172, 2016 | 11 | 2016 |
| A fast fpga-based bcd adder M Ul Haque, ZT Sworna, HM Hasan Babu, AK Biswas Circuits, Systems, and Signal Processing 37, 4384-4408, 2018 | 10 | 2018 |
| ” i think this is the most disruptive technology”: Exploring sentiments of chatgpt early adopters using twitter data,” 2022 MU Haque, I Dharmadasa, ZT Sworna, RN Rajapakse, H Ahmad arXiv preprint arXiv:2212.05856, 0 | 9 | |
| A LUT-based matrix multiplication using neural networks ZT Sworna, MU Haque, HMH Babu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1982-1985, 2016 | 6 | 2016 |
| High-speed and area-efficient LUT-based BCD multiplier design ZT Sworna, MUI Haque, DM Anisuzzaman 2018 IEEE International WIE Conference on Electrical and Computer …, 2018 | 4 | 2018 |
| An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem ZT Sworna, MU Haque, HMH Babu, L Jamal, AK Biswas 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 116-121, 2017 | 4 | 2017 |
| A fast and compact binary to BCD converter circuit N Hossain, N Hossain, ZT Sworna, MU Haque 2019 IEEE international WIE conference on electrical and computer …, 2019 | 3 | 2019 |
| An FPGA-based divider circuit using simulated annealing algorithm ZT Sworna, MU Haque, S Rahman 2018 18th International Symposium on Communications and Information …, 2018 | 3 | 2018 |
| IRP2API: Automated Mapping of Cyber Security Incident Response Plan to Security Tools’ APIs ZT Sworna, MA Babar, A Sreekumar 2023 IEEE International Conference on Software Analysis, Evolution and …, 2023 | 2 | 2023 |
| Two novel design approaches for optimized reversible multiplier circuit S Afrin, F Shihab, ZT Sworna 2019 IEEE International WIE Conference on Electrical and Computer …, 2019 | 2 | 2019 |
| Security Tools' API Recommendation Using Machine Learning. ZT Sworna, A Sreekumar, C Islam, MA Babar ENASE, 27-38, 2023 | 1 | 2023 |
| A cost-efficient look-up table based binary coded decimal adder design ZT Sworna, MU Haque, HMH Babu, L Jamal arXiv preprint arXiv:2203.09665, 2022 | 1 | 2022 |
| A compact quantum cost-efficient design of a reversible binary counter MU Haque, ZT Sworna, S Afrin, FS Shan 2019 IEEE International WIE Conference on Electrical and Computer …, 2019 | 1 | 2019 |
| Leveraging NLP for supporting automated security incident response ZT Sworna | | 2023 |
| Efficient Design of a Reversible Sorting Circuit MA Brishty, MR Talukder, FS Shan, SA Mim, MU Haque, ZT Sworna 2019 2nd International Conference on Innovation in Engineering and …, 2019 | | 2019 |
| ISVLSI 2017 Additional Reviewers A Srivastava, A Singh, A Ilic, A Barteau, A Dantas, B Ege, ... | | |
