Seuraa
Manish Pandey
Manish Pandey
Adjunct Professor, ECE Department at Carnegie Mellon University
Vahvistettu sähköpostiosoite verkkotunnuksessa andrew.cmu.edu
Nimike
Viittaukset
Viittaukset
Vuosi
Formal verification of content addressable memories using symbolic trajectory evaluation
M Pandey, R Raimi, RE Bryant, MS Abadir
Proceedings of the 34th annual Design Automation Conference, 167-172, 1997
791997
Formal verification of content addressable memories using symbolic trajectory evaluation
M Pandey, R Raimi, RE Bryant, MS Abadir
Proceedings of the 34th annual Design Automation Conference, 167-172, 1997
791997
Formal verification of PowerPC arrays using symbolic trajectory evaluation
M Pandey, R Raimi, DL Beatty, RE Bryant
33rd Design Automation Conference Proceedings, 1996, 649-654, 1996
641996
Method and mechanism for implementing electronic designs having power information specifications background
Q Wang, A Gupta, P Chen, C Chu, M Pandey, HC Tsai, S Bhatia, Y Chen, ...
US Patent 7,739,629, 2010
542010
Method and system for equivalence checking of a low power design
M Pandey, R Arora, CC Lin, HC Tsai, B Chandramouli, KY Khoo
US Patent 7,669,165, 2010
442010
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
M Pandey, RE Bryant
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
411999
PowerPC/sup (TM)/array verification methodology using formal techniques
N Ganguly, M Abadir, M Pandey
Proceedings International Test Conference 1996. Test and Design Validity …, 1996
361996
Method and system for verifying power specifications of a low power design
B Chandramouli, HC Tsai, M Pandey, CC Lin, MM Das
US Patent 7,694,251, 2010
322010
Machine learning and systems for building the next generation of EDA tools
M Pandey
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 411-415, 2018
292018
Method and system for generating design constraints
M Pandey, M Glusman, A Krstic, YW Hsieh, A Lin
US Patent 7,962,886, 2011
292011
Managing model checks of sequential designs
J Yu, M Pandey
US Patent App. 10/140,403, 2018
24*2018
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
M Pandey, RE Bryant
International Conference on Computer Aided Verification, 244-255, 1997
211997
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
M Pandey, RE Bryant
International Conference on Computer Aided Verification, 244-255, 1997
211997
Built-in self-test structures around cellular automata and counters
AK Das, M Pandey, A Gupta, PP Chaudhuri
IEE Proceedings E (Computers and Digital Techniques) 137 (4), 269-276, 1990
201990
Formal verification of memory arrays
M Pandey
Carnegie Mellon University, 1997
191997
Method and system for logic equivalence checking
M Pandey, YT Lai, B Siarkowski, KY Khoo, CC Lin
US Patent 7,266,790, 2007
152007
Formal verification of memory arrays using symbolic trajectory evaluation
M Pandey, RE Bryant
Proceedings. International Workshop on Memory Technology, Design and Testing …, 1997
151997
Enhanced symbolic simulation for efficient verification of embedded array systems
T Feng, LC Wang, KT Cheng, M Pandey, MS Abadir
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
142003
Attribute Value Generation from Product Title using Language Models
K Roy, P Goyal, M Pandey
Proceedings of The 4th Workshop on e-Commerce and NLP, 13-17, 2021
132021
RTL verification using computational complexity-based property ranking and scheduling
J Yu, M Pandey, MY Chung, A Saha
US Patent 10,521,536, 2019
132019
Järjestelmä ei voi suorittaa toimenpidettä nyt. Yritä myöhemmin uudelleen.
Artikkelit 1–20