| Field effect transistor and method for manufacturing the same CW Oh, D Park, D Kim, D Choi, K Yeo US Patent App. 11/089,371, 2005 | 70 | 2005 |
| Field effect transistor and method for manufacturing the same CW Oh, D Park, D Kim, D Choi, K Yeo US Patent 8,101,475, 2012 | 61 | 2012 |
| Damascene gate FinFET SONOS memory implemented on bulk silicon wafer CW Oh, SD Suk, YK Lee, SK Sung, JD Choe, SY Lee, DU Choi, KH Yeo, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 48 | 2004 |
| Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application EJ Yoon, SY Lee, SM Kim, MS Kim, SH Kim, L Ming, S Suk, K Yeo, CW Oh, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 40 | 2004 |
| Field effect transistor with buried gate pattern M Li, D Choi, CW Oh, D Kim, MS Kim, SH Kim, K Yeo US Patent 7,361,545, 2008 | 33 | 2008 |
| A high performance 16M DRAM on a thin film SOI HS Kim, SB Lee, DU Choi, JH Shim, KH Lee, KP Lee, KN Kim, JW Park 1995 Symposium on VLSI Technology. Digest of Technical Papers, 143-144, 1995 | 26 | 1995 |
| Method of manufacturing semiconductor device HS Kang, BK Cho, C Lee, D Choi US Patent 8,053,347, 2011 | 23 | 2011 |
| Flash memory device and programming/erasing method of the same D Choi, JD Choi, C Lee, SH Hur, MT Yu US Patent 8,134,873, 2012 | 20 | 2012 |
| Flash memory device including a dummy cell HS Kang, D Choi, C Lee, SG Kang US Patent 7,978,522, 2011 | 18 | 2011 |
| SONOS-type FinFET device using P+ poly-Si gate and high-k blocking dielectric integrated on cell array and GSL/SSL for multi-gigabit NAND flash memory SK Sung, SH Lee, B Choi, J Lee, JD Choe, E Cho, Y Ahn, D Choi, CH Lee, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 86-87, 2006 | 18 | 2006 |
| Trap layer engineered FinFET NAND flash with enhanced memory window Y Ahn, JD Choe, J Lee, D Choi, E Cho, B Choi, SH Lee, SK Sung, CH Lee, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 88-89, 2006 | 17 | 2006 |
| Floating body DRAM characteristics of silicon-on-ONO (SOONO) devices for system-on-chip (SoC) applications CW Oh, NY Kim, HJ Song, SI Hong, SH Kim, YL Choi, HJ Bae, DU Choi, ... 2007 IEEE Symposium on VLSI Technology, 168-169, 2007 | 15 | 2007 |
| Lateral integration of partially insulated and bulk MOSFETs using partial SOI process SH Kim, CW Oh, KH Yeo, DU Choi, MS Kim, SM Kim, JD Choe, J Han, ... 2005 IEEE International SOI Conference Proceedings, 174-175, 2005 | 9 | 2005 |
| Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions CW Oh, KH Yeo, MS Kim, CS Lee, DU Choi, SH Kim, SY Lee, SM Kim, ... Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat …, 2004 | 9 | 2004 |
| Field effect transistor and method for manufacturing the same CW Oh, D Park, D Kim, D Choi, K Yeo US Patent 8,415,210, 2013 | 7 | 2013 |
| Non-volatile memory devices JS Sel, JD Choi, C Lee, J Chung, HS Kang, D Choi US Patent 7,884,425, 2011 | 6 | 2011 |
| Data retention times in SOI-DRAMs HS Kim, DU Choi, SH Lee, SK Lee, JK Park, KN Kim, JW Park 1996 Symposium on VLSI Technology. Digest of Technical Papers, 126-127, 1996 | 6 | 1996 |
| Selection transistor BK Cho, HS Kang, D Choi, C Lee US Patent 7,982,246, 2011 | 5 | 2011 |
| Method of programming data in a NAND flash memory device and method of reading data in the NAND flash memory device HS Kang, C Lee, D Choi US Patent 7,911,847, 2011 | 3 | 2011 |
| Methods and Apparatus for Operating a Transistor Using a Reverse Body Bias EJ Yun, S Lee, S Kim, D Park, D Choi US Patent App. 11/461,825, 2007 | 3 | 2007 |
