| A 0.008500 /spl mu/W 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation S Hwang, J Koo, K Kim, H Lee, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (9), 2241-2248, 2013 | 104 | 2013 |
| A 1-V 10-Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascaded-equalizer for post-LPDDR4 interfaces J Song, S Hwang, HW Lee, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 65 (1), 331-342, 2017 | 40 | 2017 |
| A 1.62 Gb/s–2.7 Gb/s referenceless transceiver for DisplayPort v1. 1a with weighted phase and frequency detection J Song, I Jung, M Song, YH Kwak, S Hwang, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (2), 268-278, 2012 | 39 | 2012 |
| A self-calibrated DLL-based clock generator for an energy-aware EISC processor S Hwang, KM Kim, J Kim, SW Kim, C Kim IEEE transactions on very large scale integration (VLSI) systems 21 (3), 575-579, 2012 | 28 | 2012 |
| 34.1 an 8960-element ultrasound-on-chip for point-of-care ultrasound N Sanchez, K Chen, C Chen, D McMahill, S Hwang, J Lutsky, J Yang, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 480-482, 2021 | 27 | 2021 |
| A 3.5 GHz spread-spectrum clock generator with a memoryless Newton-Raphson modulation profile S Hwang, M Song, YH Kwak, I Jung, C Kim IEEE journal of solid-state circuits 47 (5), 1199-1208, 2012 | 24 | 2012 |
| A 1.62–5.4-Gb/s receiver for DisplayPort version 1.2 a with adaptive equalization and referenceless frequency acquisition techniques S Hwang, J Song, Y Lee, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 64 (10), 2691-2702, 2017 | 17 | 2017 |
| An 11.2-Gb/s LVDS receiver with a wide input range comparator KM Kim, S Hwang, J Song, C Kim IEEE Transactions on very large scale integration (VLSI) systems 22 (10 …, 2013 | 17 | 2013 |
| A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process YH Kwak, Y Kim, S Hwang, C Kim IEEE Transactions on Circuits and Systems I: Regular Papers 60 (2), 303-313, 2013 | 16 | 2013 |
| A 250-Mb/s to 6-Gb/s referenceless clock and data recovery circuit with clock frequency multiplier JY Kim, J Song, J You, S Hwang, SG Bae, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 650-654, 2015 | 12 | 2015 |
| A 5.4 Gb/s adaptive equalizer with unit pulse charging technique in 0.13 µm CMOS S Hwang, I Jung, J Song, C Kim 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1959-1962, 2012 | 10 | 2012 |
| A 0.076mm23.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS S Hwang, M Song, YH Kwak, I Jung, C Kim 2011 IEEE International Solid-State Circuits Conference, 360-362, 2011 | 10 | 2011 |
| 29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces Y Lee, YJ Choi, SG Bae, J Jun, J Song, S Hwang, C Kim 2017 IEEE International Solid-State Circuits Conference (ISSCC), 490-491, 2017 | 8 | 2017 |
| A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE S Hwang, S Moon, J Song, C Kim 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 8 | 2016 |
| 12-Gb/s over four balanced lines utilizing NRZ braid clock signaling with no data overhead and spread transition scheme for 8K UHD intra-panel interfaces Y Lee, Y Choi, J Song, S Hwang, SG Bae, J Jun, C Kim IEEE Journal of Solid-State Circuits 54 (2), 463-475, 2018 | 7 | 2018 |
| An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface J Song, HW Lee, SB Lim, S Hwang, Y Kim, YJ Choi, BT Chung, C Kim 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 6 | 2013 |
| A-Gb/s 1.12-Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels J Song, S Hwang, C Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016 | 5 | 2016 |
| A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13-CMOS Process J Song, S Hwang, HW Lee, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 865-869, 2014 | 5 | 2014 |
| A Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth SG Bae, S Hwang, J Song, Y Lee, C Kim IEEE Transactions on Circuits and Systems II: Express Briefs 66 (2), 192-196, 2018 | 3 | 2018 |
| A 1.69-pJ/b 14-Gb/s digital sub-sampling CDR with combined adaptive equalizer and self-error corrector Y Choi, S Hwang, Y Lee, H Park, J Choi, J Sim, C Kim IEEE Access 9, 118907-118918, 2021 | 2 | 2021 |
