Todd Austin

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David BlaauwProfessor of Electrical Engineering and Computer Science, University of MichiganVerified email at umich.edu
Valeria BertaccoProfessor, Computer Science and Engineering, University of MichiganVerified email at umich.edu
Krisztián FlautnerUtopiun LLCVerified email at utopiun.com
Dan ErnstMicrosoftVerified email at microsoft.com
Doug BurgerTechnical Fellow, Microsoft AzureVerified email at microsoft.com
Nam Sung KimW.J. ‘Jerry’ Sanders III – AMD, Inc. Endowed Chair Professor and Fellow of ACM/IEEEVerified email at illinois.edu
Brad CalderGoogleVerified email at google.com
Shidhartha DasAMDVerified email at amd.com
Sanjay PantApple Inc.Verified email at apple.com
Dennis SylvesterProfessor of Electrical Engineering and Computer Science, University of MichiganVerified email at umich.edu
Leyla NazhandaliAssociate Professor, Bradley Department of Electrical and Computer Engineering, Virginia TechVerified email at vt.edu
Richard B. BrownProfessor of ECE and CS, University of UtahVerified email at utah.edu
Jeff RingenbergUniversity of MichiganVerified email at umich.edu
Scott MahlkeProfessor, Electrical Engineering and Computer Science Dept., University of MichiganVerified email at umich.edu
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaVerified email at csail.mit.edu
Bo Zhai 翟博University of MichiganVerified email at umich.edu
Glenn ReinmanProfessor of Computer Science, UCLAVerified email at cs.ucla.edu
Salessawi Ferede YitbarekIntel CorporationVerified email at intel.com
Seokwoo LeeVisiting Assistant Professor of Finance, University of MarylandVerified email at umd.edu
Misiker Tadesse AgaUniversity of MichiganVerified email at fb.com

Todd Austin

Professor of Computer Science and Electrical Engineering, University of Michigan

Verified email at umich.edu - Homepage

Hardware Security Computer Architecture Computer Security Reliability Low-power Design


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MiBench: A free, commercially representative embedded benchmark suite MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown Proceedings of the fourth annual IEEE international workshop on workload …, 2001	4754	2001
MiBench: A free, commercially representative embedded benchmark suite MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown Proceedings of the fourth annual IEEE international workshop on workload …, 2001	4754	2001
MiBench: A free, commercially representative embedded benchmark suite MR Guthaus, JS Ringenberg, D Ernst, TM Austin, T Mudge, RB Brown Proceedings of the fourth annual IEEE international workshop on workload …, 2001	4754	2001
The SimpleScalar tool set, version 2.0 D Burger, TM Austin ACM SIGARCH computer architecture news 25 (3), 13-25, 1997	4288	1997
Rechnerarchitektur: von der digitalen Logik zum Parallelrechner AS Tanenbaum, T Austin Pearson Deutschland GmbH, 2014	2485*	2014
Structured computer organization AS Tanenbaum Pearson Education India, 2016	2441	2016
SimpleScalar: An infrastructure for computer system modeling T Austin, E Larson, D Ernst Computer 35 (2), 59-67, 2002	2324	2002
Leakage current: Moore's law meets static power NS Kim, T Austin, D Baauw, T Mudge, K Flautner, JS Hu, MJ Irwin, ... computer 36 (12), 68-75, 2003	1749	2003
Razor: A low-power pipeline based on circuit-level timing speculation D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ... Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003	1742	2003
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003	1271	2003
DIVA: A reliable substrate for deep submicron microarchitecture design TM Austin MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999	1034	1999
Evaluating future microprocessors: The simplescalar tool set D Burger, TM Austin, S Bennett University of Wisconsin-Madison Department of Computer Sciences, 1996	850	1996
Efficient detection of all pointer and array access errors TM Austin, SE Breach, GS Sohi Proceedings of the ACM SIGPLAN 1994 conference on Programming Language …, 1994	638	1994
A self-tuning DVS processor using delay-error detection and correction S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006	572	2006
Razor: circuit-level correction of timing errors for low-power operation D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner IEEE Micro 24 (6), 10-20, 2004	527	2004
Cache-conscious data placement B Calder, C Krintz, S John, T Austin Proceedings of the eighth international conference on Architectural support …, 1998	413	1998
A2: Analog malicious hardware K Yang, M Hicks, Q Dong, T Austin, D Sylvester 2016 IEEE symposium on security and privacy (SP), 18-37, 2016	288	2016
Reliable systems on unreliable fabrics T Austin, V Bertacco, S Mahlke, Y Cao IEEE Design & Test of Computers 25 (4), 322-332, 2008	285	2008
Dynamic dependency analysis of ordinary programs TM Austin, GS Sohi Proceedings of the 19th annual international symposium on Computer …, 1992	256	1992
A 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency B Zhai, L Nazhandali, J Olson, A Reeves, M Minuth, R Helfand, S Pant, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 154-155, 2006	255	2006

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