sabooh ajaz
Title
Cited by
Cited by
Year
Hand gesture tracking and recognition system using Lucas–Kanade algorithms for control of consumer electronics
P Premaratne, S Ajaz, M Premaratne
Neurocomputing 116, 242-249, 2013
502013
Autonomous vehicle monitoring & tracking system
S Ajaz, M Asim, M Ozair, M Ahmed, M Siddiqui, Z Mushtaq
2005 Student Conference on Engineering Sciences and Technology, 1-4, 2005
222005
Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for Gbit wireless communication
S Ajaz, H Lee
IET Electronics Letters 48 (19), 1246-1248, 2013
192013
Hand gesture tracking and recognition system for control of consumer electronics
P Premaratne, S Ajaz, M Premaratne
International Conference on Intelligent Computing, 588-593, 2011
162011
Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11 ad standard
S Ajaz, H Lee
2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 153-156, 2014
102014
Efficient Min-Max nonbinary LDPC decoding on GPU
HP Thi, S Ajaz, H Lee
2014 International SoC Design Conference (ISOCC), 266-267, 2014
82014
High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme
C Kim, H Yun, S Ajaz, H Lee
JSTS: Journal of Semiconductor Technology and Science 15 (3), 427-435, 2015
72015
Design and implementation of edge detection algorithm in dsPIC embedded processor
P Premaratne, S Ajaz, R Monaragala, N Bandara, M Premaratne
2010 Fifth International Conference on Information and Automation for …, 2010
72010
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes
HP Thi, S Ajaz, H Lee
Integration 59, 52-63, 2017
62017
Parallel block-layered nonbinary QC-LDPC decoding on GPU
HT Pham, S Ajaz, H Lee
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
62015
Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11 ad applications
S Ajaz, H Lee
INTEGRATION, the VLSI journal 51, 21-36, 2015
62015
An efficient radix-4 Quasi Shift Network for QC-LDPC decoders
S Ajaz, H Lee
IEICE Electronics Express, 11.20130837, 2014
42014
An area-efficient half-row pipelined layered LDPC decoder architecture
S Ajaz, TTB Nguyen, H Lee
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17 (6), 845-853, 2017
32017
High-Throughput QC-LDPC Decoder Architecture for Multi-Gigabit WPAN Systems
H Lee, S Ajaz
Journal of the Institute of Electronics and Information Engineers 50 (2 …, 2013
22013
Area efficient half row pipelined layered LDPC decoder for gigabit wireless communications
S Ajaz, H Lee
2015 International SoC Design Conference (ISOCC), 287-288, 2015
12015
Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture
S Ajaz, H Lee
전자공학회논문지 51 (10), 72-79, 2014
2014
Multi-Gb/s Multi-Mode LDPC Decoder Architecture
S Ajaz, H Lee
대한전자공학회 학술대회, 2074-2075, 2014
2014
Radix-3 Quasi Shift Network For Reconfigurable QC-LDPC Decoders
S Ajaz, H Lee
대한전자공학회 ISOCC, 376-379, 2013
2013
Design and implementation of edge detection algorithm using digital signal controller (DSC)
S Ajaz, P Premaratne, M Premaratne
International Conference on Intelligent Computing, 549-556, 2011
2011
2010 5th International Conference on Information and Automation for Sustainability, ICIAfS 2010
P Premaratne, S Ajaz, R Monaragala, N Bandara, M Premaratne, ...
2010
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