Write strategies for 2 and 4-bit multi-level phase-change memory T Nirschl, JB Philipp, TD Happ, GW Burr, B Rajendran, MH Lee, A Schrott, ... 2007 IEEE International Electron Devices Meeting, 461-464, 2007 | 350 | 2007 |
Novel one-mask self-heating pillar phase change memory T Happ, M Breitwisch, A Schrott, J Philipp, M Lee, R Cheek, T Nirschl, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 120-121, 2006 | 267 | 2006 |
Ultra-thin phase-change bridge memory device using GeSb YC Chen, CT Rettner, S Raoux, GW Burr, SH Chen, RM Shelby, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 260 | 2006 |
Novel lithography-independent pore phase change memory M Breitwisch, T Nirschl, CF Chen, Y Zhu, MH Lee, M Lamorey, GW Burr, ... 2007 IEEE Symposium on VLSI Technology, 100-101, 2007 | 145 | 2007 |
Danger to the popliteal artery in high tibial osteotomy SH Zaidi, AG Cobb, G Bentley The Journal of Bone & Joint Surgery British Volume 77 (3), 384-386, 1995 | 111 | 1995 |
Memory device S Zaidi, JC Arnold US Patent App. 11/435,594, 2007 | 70 | 2007 |
Memory device S Zaidi, JC Arnold US Patent 20,070,267,618, 2007 | 62 | 2007 |
IEEE international electron devices meeting YC Chen, CT Rettner, S Raoux, GW Burr, SH Chen, RM Shelby, ... Technical Digest 2003, 767-770, 2003 | 39 | 2003 |
Integrated circuit having a memory including a low-k dielectric material for thermal isolation T Happ, S Zaidi US Patent 7,361,925, 2008 | 37 | 2008 |
Energy adjusted write pulses in phase-change memories T Happ, Z Shoaib US Patent 7,113,424, 2006 | 31 | 2006 |
Alignment or overlay marks for semiconductor processing E Carpi, SH Zaidi US Patent 6,888,260, 2005 | 29 | 2005 |
Phase change memory J Philipp, S Zaidi US Patent App. 11/407,345, 2007 | 24 | 2007 |
Mask and method for using the mask in lithographic processing SSH Zaidi, A Gutmann, G Williams US Patent 7,030,506, 2006 | 24 | 2006 |
Metrology sensors for advanced resists SH Zaidi, SL Prins, JR McNeil, SSH Naqvi Integrated Circuit Metrology, Inspection, and Process Control VIII 2196, 341-351, 1994 | 23 | 1994 |
Low power phase change memory cell with large read signal T Happ, SH Zaidi, JB Philipp US Patent 7,973,301, 2011 | 22 | 2011 |
Memory cell having active region sized for low reset current and method of fabricating such memory cells S Zaidi US Patent App. 11/487,876, 2008 | 20 | 2008 |
Asynchronous collaboration session linked to a synchronous collaboration session D Sylvain US Patent 10,015,212, 2018 | 17* | 2018 |
Int. Electron Devices Meeting YC Chen, CT Rettner, S Raoux, GW Burr, SH Chen, RM Shelby, ... IEEE, Piscataway, 2006 | 17 | 2006 |
Integrated circuit including silicide region to inhibit parasitic currents B Rajendran, SH Zaidi US Patent 7,863,610, 2011 | 15 | 2011 |
Patterning of N:Ge2Sb2Te5 Films and the Characterization of Etch Induced Modification for Non-Volatile Phase Change Memory Applications EA Joseph, TD Happ, SH Chen, S Raoux, CF Chen, M Breitwisch, ... 2008 International Symposium on VLSI Technology, Systems and Applications …, 2008 | 15 | 2008 |