| Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach D Sisejkovic, F Merchant, LM Reimann, H Srivastava, A Hallawa, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-26, 2021 | 62 | 2021 |
| Deceptive logic locking for hardware integrity protection against machine learning attacks D Sisejkovic, F Merchant, LM Reimann, R Leupers IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 37 | 2021 |
| Logic locking at the frontiers of machine learning: A survey on developments and opportunities D Sisejkovic, LM Reimann, E Moussavi, F Merchant, R Leupers 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 22 | 2021 |
| Qflow: Quantitative information flow for security-aware hardware design in verilog LM Reimann, L Hanel, D Sisejkovic, F Merchant, R Leupers 2021 IEEE 39th International Conference on Computer Design (ICCD), 603-607, 2021 | 20 | 2021 |
| A secure hardware-software solution based on RISC-V, logic locking and microkernel D Šišejković, F Merchant, LM Reimann, R Leupers, M Giacometti, ... Proceedings of the 23th International Workshop on Software and Compilers for …, 2020 | 18 | 2020 |
| Scaling logic locking schemes to multi-module hardware designs D Šišejković, F Merchant, LM Reimann, R Leupers, S Kegreiß Architecture of Computing Systems–ARCS 2020: 33rd International Conference …, 2020 | 13 | 2020 |
| Andromeda: An fpga based risc-v mpsoc exploration framework F Merchant, D Sisejkovic, LM Reimann, K Yasotharan, T Grass, ... 2021 34th International Conference on VLSI Design and 2021 20th …, 2021 | 6 | 2021 |
| ZuSE Ki-Avf: application-specific AI processor for intelligent sensor signal processing in autonomous driving GB Thieu, S Gesper, G Payá-Vayá, C Riggers, O Renke, T Fiedler, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 5 | 2023 |
| Quantitative information flow for hardware: Advancing the attack landscape LM Reimann, S Erdönmez, D Sisejkovic, R Leupers 2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS), 1-4, 2023 | 3 | 2023 |
| QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL LM Reimann, A Prashar, C Ghinami, R Pelke, D Sisejkovic, F Merchant, ... arXiv preprint arXiv:2401.17819, 2024 | | 2024 |
| Evaluation of the RISC-V Floating Point Extensions N Zurstrassen, LM Reimann, N Bosbach, L Juenger, R Leupers DVCon Europe 2023; Design and Verification Conference and Exhibition Europe …, 2023 | | 2023 |
| SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors LM Reimann, J Wiesner, D Sisejkovic, F Merchant, R Leupers 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration …, 2023 | | 2023 |
| Automated Information Flow Analysis for Integrated Computing-in-Memory Modules LM Reimann, F Staudigl, R Leupers 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS), 1-5, 2023 | | 2023 |
| 2023ECOSYSTEM FOR TRUSTWORTHY IT D Sisejkovic, LM Reimann, M Malenko, R Leupers | | 2023 |
Rainer LeupersRWTH AachenVerified email at ice.rwth-aachen.de
