BerkMin: A fast and robust SAT-solver E Goldberg, Y Novikov Discrete Applied Mathematics 155 (12), 1549-1561, 2007 | 1175 | 2007 |
Verification of proofs of unsatisfiability for CNF formulas E Goldberg, Y Novikov 2003 Design, Automation and Test in Europe Conference and Exhibition, 886-891, 2003 | 285 | 2003 |
Using SAT for combinational equivalence checking EI Goldberg, MR Prasad, RK Brayton Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 284 | 2001 |
Quantifier elimination by dependency sequents E Goldberg, P Manolios Formal Methods in System Design 45, 111-143, 2014 | 27 | 2014 |
Negative thinking in branch-and-bound: the case of unate covering EI Goldberg, LP Carloni, T Villa, RK Brayton, AL Sangiovanni-Vincentelli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000 | 24 | 2000 |
Using problem symmetry in search based satisfiability algorithms EI Goldberg, MR Prasad, RK Brayton Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 21 | 2002 |
Quantifier elimination via clause redundancy E Goldberg, P Manolios 2013 Formal Methods in Computer-Aided Design, 85-92, 2013 | 20 | 2013 |
Timing analysis with implicitly specified false paths E Goldberg, A Saldanha International conference on VLSI design, 2000 | 20 | 2000 |
On Bridging Simulation and Formal Verification E Goldberg Verification, Model Checking, and Abstract Interpretation 4905 (Lecture …, 2008 | 19 | 2008 |
Negative thinking by incremental problem solving: application to unate covering Carloni, Villa, Brayton 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 19 | 1997 |
Efficient verification of multi-property designs (the benefit of wrong assumptions) E Goldberg, M Güdemann, D Kroening, R Mukherjee 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 43-48, 2018 | 16 | 2018 |
Partial quantifier elimination E Goldberg, P Manolios Hardware and Software: Verification and Testing: 10th International Haifa …, 2014 | 16 | 2014 |
Theory and algorithms for face hypercube embedding EI Goldberg, T Villa, RK Brayton, AL Sangiovanni-Vincentelli IEEE transactions on computer-aided design of integrated circuits and …, 1998 | 15 | 1998 |
Equivalence checking by logic relaxation E Goldberg 2016 Formal Methods in Computer-Aided Design (FMCAD), 49-56, 2016 | 10 | 2016 |
Canonical TBDD’s and their application to combinational verification EI Goldberg, Y Kukimoto, RK Brayton Proc. IWLS, 1997 | 10 | 1997 |
Method and system for solving satisfiability problems E Goldberg, Y Novikov US Patent 7,356,519, 2008 | 9 | 2008 |
Toggle equivalence preserving logic synthesis E Goldberg, K Gulati US Patent 7,600,211, 2009 | 5 | 2009 |
Combinational verification based on high-level functional specifications EI Goldberg, Y Kukimoto, RK Brayton Proceedings Design, Automation and Test in Europe, 803-808, 1998 | 5 | 1998 |
A fast and robust exact algorithm for face embedding Villa, Brayton 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 5 | 1997 |
Partial quantifier elimination and property generation E Goldberg Computer Aided Verification 13965 (Lecture Notes in Computer Science), 2023 | 4 | 2023 |