Keshab K. Parhi
Keshab K. Parhi
Professor of Electrical & Computer Engineering, University of Minnesota
Verified email at umn.edu - Homepage
Title
Cited by
Cited by
Year
VLSI digital signal processing systems: design and implementation
KK Parhi
John Wiley & Sons, 1999
2329*1999
High-speed VLSI architectures for the AES algorithm
X Zhang, KK Parhi
IEEE transactions on very large scale integration (VLSI) systems 12 (9), 957-967, 2004
5092004
VLSI architectures for discrete wavelet transforms
KK Parhi, T Nishitani
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (2), 191-202, 1993
5081993
Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding
KK Parhi, DG Messerschmitt
IEEE Transactions on Computers, 178-195, 1991
4511991
Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition
KK Parhi, DG Messerschmitt
IEEE Transactions on Acoustics, Speech, and Signal Processing 37 (7), 1099-1117, 1989
4341989
Seizure prediction with spectral power of EEG using cost‐sensitive support vector machines
Y Park, L Luo, KK Parhi, T Netoff
Epilepsia 52 (10), 1761-1770, 2011
3042011
Low-energy digit-serial/parallel finite field multipliers
L Song, KK Parhi
Journal of VLSI signal processing systems for signal, image and video …, 1998
2921998
Distributed scheduling of broadcasts in a radio network
R Ramaswami, KK Parhi
IEEE INFOCOM'89, Proceedings of the Eighth Annual Joint Conference of the …, 1989
2741989
Algorithm transformation techniques for concurrent processors
KK Parhi
Proceedings of the IEEE 77 (12), 1879-1895, 1989
2561989
Design of low-error fixed-width modified booth multiplier
KJ Cho, KC Lee, JG Chung, KK Parhi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 522-531, 2004
2312004
Synthesis of control circuits in folded pipelined DSP architectures
KK Parhi, CY Wang, AP Brown
IEEE Journal of Solid-State Circuits 27 (1), 29-43, 1992
2221992
Small area parallel Chien search architectures for long BCH codes
Y Chen, KK Parhi
Ieee Transactions on Very Large Scale Integration (VLSI) Systems 12 (5), 545-549, 2004
214*2004
A systematic approach for design of digit-serial signal processing architectures
KK Parhi
IEEE Transactions on Circuits and Systems 38 (4), 358-375, 1991
2141991
DREAM: diabetic retinopathy analysis using machine learning
S Roychowdhury, DD Koozekanani, KK Parhi
IEEE journal of biomedical and health informatics 18 (5), 1717-1728, 2013
2092013
Efficient semisystolic architectures for finite-field arithmetic
SK Jain, L Song, KK Parhi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (1), 101-113, 1998
2081998
Blood vessel segmentation of fundus images by major vessel extraction and subimage classification
S Roychowdhury, DD Koozekanani, KK Parhi
IEEE journal of biomedical and health informatics 19 (3), 1118-1128, 2014
2012014
Overlapped message passing for quasi-cyclic low-density parity check codes
Y Chen, KK Parhi
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (6), 1106-1113, 2004
1912004
Low-area/power parallel FIR digital filter implementations
DA Parker, KK Parhi
Journal of VLSI signal processing systems for signal, image and video …, 1997
190*1997
A 54 mbps (3, 6)-regular FPGA LDPC decoder
T Zhang, KK Parhi
IEEE workshop on signal processing systems, 127-132, 2002
1792002
Implementation approaches for the advanced encryption standard algorithm
X Zhang, KK Parhi
IEEE Circuits and systems Magazine 2 (4), 24-46, 2002
1762002
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