| Efficient approaches for designing reversible binary coded decimal adders AK Biswas, MM Hasan, AR Chowdhury, HMH Babu Microelectronics journal 39 (12), 1693-1703, 2008 | 161 | 2008 |
| Synthesis of full-adder circuit using reversible logic HMH Babu, MR Islam, SMA Chowdhury, AR Chowdhury 17th International Conference on VLSI Design. Proceedings., 757-760, 2004 | 112 | 2004 |
| Reversible logic synthesis for minimization of full-adder circuit HMH Babu, MR Islam, AR Chowdhury, SMA Chowdhury Euromicro Symposium on Digital System Design, 2003. Proceedings., 50-54, 2003 | 95 | 2003 |
| Design of a compact reversible binary coded decimal adder circuit HMH Babu, AR Chowdhury Journal of systems architecture 52 (5), 272-282, 2006 | 76 | 2006 |
| Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder HMH Babu, AR Chowdhury 18th International Conference on VLSI Design Held Jointly with 4th …, 2005 | 73 | 2005 |
| Efficient design of shift registers using reversible logic NM Nayeem, MA Hossain, L Jamal, HMH Babu 2009 International Conference on Signal Processing Systems, 474-478, 2009 | 56 | 2009 |
| Design of optimal reversible carry lookahead adder with optimal garbage and quantum cost L Jamal, M Shamsujjoha, HMH Babu International Journal of Engineering and Technology 2 (1), 44-50, 2012 | 49 | 2012 |
| Efficient reversible Montgomery multiplier and its application to hardware cryptography NM Nayeem, L Jamal, HMH Babu Journal of computer science 5 (1), 49, 2009 | 48 | 2009 |
| An efficient design of a reversible barrel shifter I Hashmi, HMH Babu 2010 23rd International Conference on VLSI Design, 93-98, 2010 | 46 | 2010 |
| Design of a compact reversible random access memory F Sharmin, MMA Polash, M Shamsujjoha, L Jamal, HMH Babu 4th IEEE International Conference on Computer Science and Information …, 2011 | 44 | 2011 |
| A novel approach to design BCD adder and carry skip BCD adder AK Biswas, MM Hasan, M Hasan, AR Chowdhury, HMH Babu 21st international conference on VLSI design (VLSID 2008), 566-571, 2008 | 32 | 2008 |
| A low power fault tolerant reversible decoder using mos transistors M Shamsujjoha, HMH Babu 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 31 | 2013 |
| Novel reversible division hardware NM Nayeem, A Hossain, M Haque, L Jamal, HMH Babu 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 1134 …, 2009 | 26 | 2009 |
| A new approach to synthesize multiple-output functions using reversible programmable logic array AR Chowdhury, R Nazmul 19th International Conference on VLSI Design held jointly with 5th …, 2006 | 22 | 2006 |
| An optimal design of a fault tolerant reversible multiplier L Jamal, MM Rahman, HMH Babu 2013 IEEE International SOC Conference, 37-42, 2013 | 17 | 2013 |
| Design of reversible fault tolerant programmable logic arrays with vector orientation R Rahman, L Jamal, HMH Babu International Journal of Information and Communication Technology Research 1 (8), 2011 | 17 | 2011 |
| On the realization of reversible full-adder circuit HMH Babu, MR Islam, AR Chowdhury, SMA Chowdhury International Conference on Computer and Information Technology, 880-883, 2003 | 17 | 2003 |
| Approach to design a compact reversible low power binary comparator HMH Babu, N Saleheen, L Jamal, SM Sarwar, T Sasao IET Computers & Digital Techniques 8 (3), 129-139, 2014 | 16 | 2014 |
| Realization of reversible logic in DNA computing A Sarker, T Ahmed, SMM Rashid, S Anwar, L Jaman, N Tara, MM Alam, ... 2011 IEEE 11th International Conference on Bioinformatics and Bioengineering …, 2011 | 16 | 2011 |
| An efficient approach to design a reversible control unit of a processor L Jamal, MM Alam, HMH Babu Sustainable Computing: Informatics and Systems 3 (4), 286-294, 2013 | 15 | 2013 |
