| Fault injection techniques and tools for embedded systems reliability evaluation A Benso, P Prinetto Springer Science & Business Media, 2003 | 311 | 2003 |
| GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuits F Corno, P Prinetto, M Rebaudengo, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996 | 183 | 1996 |
| Formal verification of hardware correctness: Introduction and survey of current research P Camurati, P Prinetto Computer 21 (7), 8-19, 1988 | 163 | 1988 |
| A test pattern generation methodology for low power consumption E Corno, P Prinetto, M Rebaudengo, MS Reorda Proceedings. 16th IEEE VLSI Test Symposium (Cat. No. 98TB100231), 453-457, 1998 | 141 | 1998 |
| A diagnostic test pattern generation algorithm P Camurati, D Medina, P Prinetto, MS Reorda Proceedings. International Test Conference 1990, 52-58, 1990 | 132 | 1990 |
| An automatic test pattern generator for large sequential circuits based on genetic algorithms P Prinetto, M Rebaudengo, MS Reorda Proceedings., International Test Conference, 240-249, 1995 | 127 | 1995 |
| AC/C++ source-to-source compiler for dependable applications A Benso, S Chiusano, P Prinetto, L Tagliaferri Proceeding International Conference on Dependable Systems and Networks. DSN …, 2000 | 122 | 2000 |
| Testability analysis and ATPG on behavioral RT-level VHDL F Corno, P Prinetto, MS Reorda Proceedings International Test Conference 1997, 753-759, 1997 | 107 | 1997 |
| Fast sequential circuit test generation using high-level and gate-level techniques EM Rudnick, R Vietti, A Ellis, F Corno, P Prinetto, MS Reorda Proceedings Design, Automation and Test in Europe, 570-576, 1998 | 89 | 1998 |
| A watchdog processor to detect data and control flow errors A Benso, S Di Carlo, G Di Natale, P Prinetto 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 144-148, 2003 | 88 | 2003 |
| New static compaction techniques of test sequences for sequential circuits F Corno, P Prinetto, M Rebaudengo, MS Reorda Proceedings European Design and Test Conference. ED & TC 97, 37-43, 1997 | 74 | 1997 |
| Advanced techniques for GA-based sequential ATPGs F Corno, P Prinetto, M Rebaudengo, MS Reorda, R Mosca Proceedings ED&TC European Design and Test Conference, 375-379, 1996 | 72 | 1996 |
| Diagnosis oriented test pattern generation P Camurati, A Lioy, P Prinetto, MS Reorda Proceedings of the European Design Automation Conference, 470,471,472,473 …, 1990 | 69 | 1990 |
| Industrial BIST of embedded RAMs P Camurati, P Prinetto, MS Reorda, S Barbagallo, A Burri, D Medina IEEE Design & Test of Computers 12 (03), 86-95, 1995 | 67 | 1995 |
| An on-line BIST RAM architecture with self-repair capabilities A Benso, S Chiusano, G Di Natale, P Prinetto IEEE Transactions on Reliability 51 (1), 123-128, 2002 | 66 | 2002 |
| Control-flow checking via regular expressions A Benso, S Di Carlo, G Di Natale, P Prinetto, L Tagliaferri Proceedings 10th Asian Test Symposium, 299-303, 2001 | 66 | 2001 |
| Software-based self-test of set-associative cache memories S Di Carlo, P Prinetto, A Savino IEEE Transactions on Computers 60 (7), 1030-1044, 2010 | 61 | 2010 |
| STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability EI Vatajelu, GD Natale, M Barbareschi, L Torres, M Indaco, P Prinetto ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-21, 2016 | 59 | 2016 |
| GARDA: A diagnostic ATPG for large synchronous sequential circuits F Corno, P Prinetto, M Rebaudengo, MS Reorda Proceedings the European Design and Test Conference. ED&TC 1995, 267-271, 1995 | 58 | 1995 |
| HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs A Benso, S Chiusano, S Di Carlo, P Prinetto, F Ricciato, M Spadari, ... Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000 | 55 | 2000 |
