| Hardware-software co-design of slimmed optical neural networks Z Zhao, D Liu, M Li, Z Ying, L Zhang, B Xu, B Yu, RT Chen, DZ Pan Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | 52 | 2019 |
| Prim-Dijkstra revisited: Achieving superior timing-driven routing trees CJ Alpert, WK Chow, K Han, AB Kahng, Z Li, D Liu, S Venkatesh Proceedings of the 2018 International Symposium on Physical Design, 10-17, 2018 | 52 | 2018 |
| Device layer-aware analytical placement for analog circuits B Xu, S Li, CW Pui, D Liu, L Shen, Y Lin, N Sun, DZ Pan Proceedings of the 2019 International Symposium on Physical Design, 19-26, 2019 | 34 | 2019 |
| TILA-S: Timing-driven incremental layer assignment avoiding slew violations D Liu, B Yu, S Chowdhury, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 25 | 2017 |
| OSFA: A new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Singh, J Um, DZ Pan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 19 | 2016 |
| OPERON: optical-electrical power-efficient route synthesis for on-chip signals D Liu, Z Zhao, Z Wang, Z Ying, RT Chen, DZ Pan Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 17 | 2018 |
| TILA: Timing-driven incremental layer assignment B Yu, D Liu, S Chowdhury, DZ Pan 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 110-117, 2015 | 16 | 2015 |
| OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions S Roy, D Liu, J Um, DZ Pan Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 16 | 2015 |
| Incremental layer assignment for critical path timing D Liu, B Yu, S Chowdhury, DZ Pan Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 14 | 2016 |
| Exploiting wavelength division multiplexing for optical logic synthesis Z Zhao, D Liu, Z Ying, B Xu, C Feng, RT Chen, DZ Pan 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 13 | 2019 |
| Synergistic topology generation and route synthesis for on-chip performance-critical signal groups D Liu, B Yu, V Livramento, S Chowdhury, D Ding, H Vo, A Sharma, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 12 | 2018 |
| Incremental layer assignment driven by an external signoff timing engine V Livramento, D Liu, S Chowdhury, B Yu, X Xu, DZ Pan, JL Güntzel, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 7 | 2016 |
| Streak: Synergistic topology generation and route synthesis for on-chip performance-critical signal groups D Liu, V Livramento, S Chowdhury, D Ding, H Vo, A Sharma, DZ Pan Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 6 | 2017 |
| Routing congestion based on layer-assigned net and placement blockage G Posser, MC Yildiz, WH Liu, C Wing-Kai, Z Li, D Liu US Patent 10,997,352, 2021 | 4 | 2021 |
| Incremental layer assignment for timing optimization D Liu, B Yu, S Chowdhury, DZ Pan ACM Transactions on Design Automation of Electronic Systems (TODAES) 22 (4 …, 2017 | 4 | 2017 |
| Routing tree topology generation JR Gao, TA Newton, D Liu, MC Yildiz, CJ Alpert, Z Li US Patent 10,289,795, 2019 | 3 | 2019 |
| Pipeline-based scheduling for heterogeneous multi-core systems D Liu, Y Wang, Z Yu, X Zeng, D Zhou 2012 IEEE 11th International Conference on Solid-State and Integrated …, 2012 | 3 | 2012 |
| Layer assignment and routing optimization for advanced technologies D Liu The University of Texas at Austin, 2018 | 1 | 2018 |
| System and method for evaluating spanning trees CJ Alpert, Z Li, WK Chow, WH Liu, D Liu US Patent 9,785,738, 2017 | 1 | 2017 |
| Containment Domains Semantics M Sullivan, I Lee, J Chung, S Zhang, SL Gong, D Liu, M LeBeane, M Erez | 1 | 2013 |
David Z. PanProfessor, Silicon Labs Endowed Chair, ECE Dept., University of Texas at AustinVahvistettu sähköpostiosoite verkkotunnuksessa ece.utexas.edu
