| 50 years of CORDIC: Algorithms, architectures, and applications PK Meher, J Valls, TB Juang, K Sridharan, K Maharatna IEEE Transactions on Circuits and Systems I: Regular Papers 56 (9), 1893-1907, 2009 | 706 | 2009 |
| The use of CORDIC in software defined radios: A tutorial J Valls, T Sansaloni, A Perez-Pascual, V Torres, V Almenar IEEE communications magazine 44 (9), 46-50, 2006 | 128 | 2006 |
| Evaluation of CORDIC algorithms for FPGA design J Valls, M Kuhlmann, KK Parhi Journal of VLSI signal processing systems for signal, image and video …, 2002 | 121 | 2002 |
| Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor F Angarita, J Valls, V Almenar, V Torres IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 2150-2158, 2014 | 96 | 2014 |
| A study about FPGA-based digital filters J Valls, MM Peiró, T Sansaloni, E Boemo 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and …, 1998 | 91 | 1998 |
| Efficient pipeline FFT processors for WLAN MIMO-OFDM systems T Sansaloni, A Perez-Pascual, V Torres, J Valls Electronics Letters 41 (19), 1043-1044, 2005 | 87 | 2005 |
| Low cost hardware implementation of logarithm approximation R Gutierrez, J Valls IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (12 …, 2010 | 71 | 2010 |
| Simplified trellis min–max decoder architecture for nonbinary low-density parity-check codes JO Lacruz, F García-Herrero, D Declercq, J Valls IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014 | 51 | 2014 |
| Area-efficient FPGA-based FFT processor T Sansaloni, A Perez-Pascual, J Valls Electronics Letters 39 (19), 1, 2003 | 48 | 2003 |
| One minimum only trellis decoder for non-binary low-density parity-check codes JO Lacruz, F García-Herrero, J Valls, D Declercq IEEE transactions on circuits and systems I: regular papers 62 (1), 177-184, 2014 | 45 | 2014 |
| Non-binary LDPC decoder based on symbol flipping with multiple votes F Garcia-Herrero, D Declercq, J Valls IEEE Communications Letters 18 (5), 749-752, 2014 | 41 | 2014 |
| FFT spectrum analyzer project for teaching digital signal processing with FPGA devices T Sansaloni, A Perez-Pascual, V Torres, V Almenar, JF Toledo, J Valls IEEE Transactions on education 50 (3), 229-235, 2007 | 41 | 2007 |
| FPGA implementation of an IF transceiver for OFDM-based WLAN MJ Canet, F Vicedo, V Almenar, J Valls IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004., 227-232, 2004 | 34 | 2004 |
| Reduced-complexity nonbinary LDPC decoder for high-order Galois fields based on trellis min–max algorithm JO Lacruz, F García-Herrero, MJ Canet, J Valls IEEE Transactions on very large scale integration (VLSI) Systems 24 (8 …, 2016 | 33 | 2016 |
| High-speed RS (255, 239) decoder based on LCC decoding F Garcia-Herrero, J Valls, PK Meher Circuits, Systems, and Signal Processing 30, 1643-1669, 2011 | 33 | 2011 |
| Optimisation of direct digital frequency synthesisers based on CORDIC F Cardells-Tormo, J Valls-Coquillat Electronics Letters 37 (21), 1278-1280, 2001 | 33 | 2001 |
| Hardware architecture of a Gaussian noise generator based on the inversion method R Gutierrez, V Torres, J Valls IEEE Transactions on Circuits and Systems II: Express Briefs 59 (8), 501-505, 2012 | 32 | 2012 |
| Design of a digital front-end transmitter for OFDM-WLAN systems using FPGA MJ Canet, F Vicedo, J Valls, V Almenar First International Symposium on Control, Communications and Signal …, 2004 | 29 | 2004 |
| FPGA-implementation of atan (Y/X) based on logarithmic transformation and LUT-based techniques R Gutierrez, V Torres, J Valls Journal of Systems Architecture 56 (11), 588-596, 2010 | 28 | 2010 |
| Low latency T-EMS decoder for non-binary LDPC codes E Li, F García-Herrero, D Declercq, K Gunnam, JO Lacruz, J Valls 2013 Asilomar Conference on Signals, Systems and Computers, 831-835, 2013 | 26 | 2013 |
