Oğuz Ergin
Oğuz Ergin
Vahvistettu sähköpostiosoite verkkotunnuksessa - Kotisivu
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
JS Kim, D Senol Cali, H Xin, D Lee, S Ghose, M Alser, H Hassan, O Ergin, ...
BMC genomics 19 (2), 23-40, 2018
Impact of parameter variations on circuits and microarchitecture
OS Unsal, JW Tschanz, K Bowman, V De, X Vera, A Gonzalez, O Ergin
IEEE Micro 26 (6), 30-39, 2006
ChargeCache: Reducing DRAM latency by exploiting row access locality
H Hassan, G Pekhimenko, N Vijaykumar, V Seshadri, D Lee, O Ergin, ...
IEEE International Symposium on High Performance Computer Architecture (HPCA …, 2016
SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies
H Hassan, N Vijaykumar, S Khan, S Ghose, K Chang, G Pekhimenko, ...
IEEE International Symposium on High Performance Computer Architecture (HPCA …, 2017
Register packing: Exploiting narrow-width operands for reducing register file pressure
O Ergin, D Balkan, K Ghose, D Ponomarev
ACM/IEEE 37th International Symposium on Microarchitecture (MICRO), 304-315, 2004
GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping
M Alser, H Hassan, H Xin, O Ergin, O Mutlu, C Alkan
Bioinformatics 33 (21), 3355-3363, 2017
Increasing processor performance through early register release
O Ergin, D Balkan, D Ponomarev, K Ghose
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
Enhancing reliability of a many-core processor
X Vera, O Unsal, O Ergin, J Abella, A González
US Patent 8,074,110, 2011
Energy efficient comparators for superscalar datapaths
DV Ponomarev, G Kucuk, O Ergin, K Ghose
IEEE Transactions on Computers 53 (7), 892-904, 2004
Exploiting narrow values for soft error tolerance
O Ergin, O Unsal, X Vera, A Gonzalez
IEEE Computer Architecture Letters 5 (2), 12-12, 2006
Energy-efficient issue queue design
DV Ponomarev, G Kucuk, O Ergin, K Ghose, PM Kogge
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (5), 789-800, 2003
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
A Olgun, M Patel, AG Yağlıkçı, H Luo, N Kim, Jeremie S., Bostancı, ...
ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA …, 2021
User-specific skin temperature-aware DVFS for smartphones
B Egilmez, G Memik, S Ogrenci-Memik, O Ergin
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
Compiler directed early register release
TM Jones, MFR O'Boyle, J Abella, A Gonzalez, O Ergin
Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th …, 2005
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
B Salami, EB Onural, IE Yuksel, F Koc, O Ergin, AC Kestelman, O Unsal, ...
50th Annual IEEE/IFIP International Conference on Dependable Systems and …, 2020
Evaluating the effects of compiler optimisations on AVF
TM Jones, MFP O’Boyle, O Ergin
Workshop on interaction between compilers and computer architecture …, 2008
Reducing datapath energy through the isolation of short-lived operands
D Ponomarev, G Kucuk, O Ergin, K Ghose
2003 12th International Conference on Parallel Architectures and Compilation …, 2003
Dynamically estimating lifetime of a semiconductor device
X Vera, J Abella, O Unsal, O Ergin, A González
US Patent 8,151,094, 2012
Energy-efficient register caching with compiler assistance
TM Jones, MFP O'Boyle, J Abella, A González, O Ergin
ACM Transactions on Architecture and Code Optimization (TACO) 6 (4), 1-23, 2009
Refueling: Preventing Wire Degradation due to Electromigration
J Abella, X Vera, OS Unsal, O Ergin, A González, JW Tschanz
IEEE Micro 28 (6), 37-46, 2008
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Artikkelit 1–20