Saša Tomić
Saša Tomić
DFINITY
Vahvistettu sähköpostiosoite verkkotunnuksessa dfinity.org
Nimike
Viittaukset
Viittaukset
Vuosi
EazyHTM: eager-lazy hardware transactional memory
S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ...
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1442009
Vertical sub-micron CMOS transistors on (110),(111),(311),(511), and higher order surfaces of bulk. SOI and thin film structures and method of forming same
L Forbes, W Noble, A Reinberg
US Patent App. 10/222,997, 2004
332004
Multi-lug socket tool
L Boston
US Patent 6,668,685, 2003
262003
The velox transactional memory stack
P Felber, E Riviere, WM Moreira, D Harmanci, P Marlier, S Diestelhorst, ...
Micro, IEEE 30 (5), 76-87, 2010
24*2010
Facing target assembly and sputter deposition apparatus
C Koh, SH Sawasaki, J Shi, YR Cheng
US Patent 6,689,253, 2004
21*2004
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
192018
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic
US Patent 9,563,373, 2017
182017
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
182016
A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory
E Akpinar, S Tomić, A Cristal, O Unsal, V Mateo
TRANSACT, 2011
182011
Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 9,632,927, 2017
172017
Dynamic filtering: multi-purpose architecture support for language runtime systems
T Harris, S Tomic, A Cristal, O Unsal
ACM SIGARCH Computer Architecture News 38 (1), 39-52, 2010
172010
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent 10,013,169, 2018
142018
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent 10,013,169, 2018
142018
Health-binning: Maximizing the performance and the endurance of consumer-level NAND flash
RA Pletka, S Tomić
Proceedings of the 9th ACM International on Systems and Storage Conference, 1-10, 2016
142016
Non-volatile memory controller cache architecture with support for separation of data streams
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic, ...
US Patent 9,779,021, 2017
112017
Method and device for managing a memory
N Ioannou, I Koltsidas, RA Pletka, S Tomic, TD Weigold
US Patent 9,760,309, 2017
112017
Storage array management employing a merged background management process
CJ Camp, TJ Fisher, AD Fry, N Ioannou, RA Pletka, LT Simmons, S Tomic
US Patent 10,365,859, 2019
102019
Endurance enhancement scheme using memory re-evaluation
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, R Pletka, S Tomic
US Patent 10,339,048, 2019
92019
Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,583,205, 2017
92017
Double balanced FET mixer with high IP3 and IF response down to DC levels
D Gamliel
US Patent 6,957,055, 2005
92005
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