Borivoje Nikolic
Borivoje Nikolic
Vahvistettu sähköpostiosoite verkkotunnuksessa berkeley.edu - Kotisivu
Nimike
Viittaukset
Viittaukset
Vuosi
Digital integrated circuits: a design perspective
JM Rabaey, AP Chandrakasan, B Nikolić
Pearson education, 2003
84002003
Introduction to stochastic processes in biostatistics
CL Chiang
2511*1968
New generation of predictive technology model for sub-45 nm early design exploration
W Zhao, Y Cao
IEEE Transactions on Electron Devices 53 (11), 2816-2823, 2006
13752006
Improved sense-amplifier-based flip-flop: Design and measurements
B Nikolic, VG Oklobdzija, V Stojanovic, W Jia, JKS Chiu, MMT Leung
IEEE Journal of Solid-State Circuits 35 (6), 876-884, 2000
5162000
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
Y Chiu, PR Gray, B Nikolic
IEEE Journal of Solid-State Circuits 39 (12), 2139-2151, 2004
3602004
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters
Y Chiu, CW Tsang, B Nikolic, PR Gray
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (1), 38-46, 2004
2432004
Methods for true energy-performance optimization
D Markovic, V Stojanovic, B Nikolic, MA Horowitz, RW Brodersen
IEEE Journal of Solid-State Circuits 39 (8), 1282-1293, 2004
2392004
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
D Maksimovic, VG Oklobdzija, B Nikolic, KW Current
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (4), 460-463, 2000
2362000
Level conversion for dual-supply systems
F Ishihara, F Sheikh, B Nikolic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 185-195, 2004
2292004
FinFET-based SRAM design
Z Guo, S Balasubramanian, R Zlatanovici, TJ King, B Nikolić
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
2142005
A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS
D Stepanovic, B Nikolic
IEEE Journal of Solid-State Circuits 48 (4), 971-982, 2013
2042013
An efficient 10GBASE-T ethernet LDPC decoder design with low error floors
Z Zhang, V Anantharam, MJ Wainwright, B Nikolic
IEEE Journal of Solid-State Circuits 45 (4), 843-855, 2010
2032010
Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes
L Dolecek, Z Zhang, V Anantharam, MJ Wainwright, B Nikolic
IEEE Transactions on Information Theory 56 (1), 181-201, 2009
2012009
High throughput low-density parity-check decoder architectures
E Yeo, P Pakzad, B Nikolic, V Anantharam
GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No. 01CH37270 …, 2001
1912001
Analysis and design of low-energy flip-flops
D Markovic, B Nikolic, R Brodersen
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
1872001
Digital integrated circuits-A design perspective
JM Rabey, A Chandrakasan, B Nikolic
Prentice Hall, 1996
1651996
VLSI architectures for iterative decoders in magnetic recording channels
E Yeo, P Pakzad, B Nikolic, V Anantharam
IEEE Transactions on Magnetics 37 (2), 748-755, 2001
1602001
A design environment for high-throughput low-power dedicated signal processing systems
WR Davis, N Zhang, K Camera, D Markovic, T Smilkstein, MJ Ammer, ...
IEEE Journal of Solid-State Circuits 37 (3), 420-431, 2002
1522002
Methods for true power minimization
RW Brodersen, MA Horowitz, D Markovic, B Nikolic, V Stojanovic
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
1482002
Large-scale SRAM variability characterization in 45 nm CMOS
Z Guo, A Carlson, LT Pang, KT Duong, TJK Liu, B Nikolic
IEEE Journal of Solid-State Circuits 44 (11), 3174-3192, 2009
1472009
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Artikkelit 1–20