Seuraa
Asit Mishra
Asit Mishra
Nvidia
Vahvistettu sähköpostiosoite verkkotunnuksessa nvidia.com - Kotisivu
Nimike
Viittaukset
Viittaukset
Vuosi
From high-level deep neural models to FPGAs
H Sharma, J Park, D Mahajan, E Amaro, JK Kim, C Shao, A Mishra, ...
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
6582016
Towards characterizing cloud backend workloads: insights from google compute clusters
AK Mishra, JL Hellerstein, W Cirne, CR Das
ACM SIGMETRICS Performance Evaluation Review 37 (4), 34-41, 2010
5262010
Accelerating binarized neural networks: Comparison of FPGA, CPU, GPU, and ASIC
E Nurvitadhi, D Sheffield, J Sim, A Mishra, G Venkatesh, D Marr
2016 International Conference on Field-Programmable Technology (FPT), 77-84, 2016
4342016
Apprentice: Using knowledge distillation techniques to improve low-precision network accuracy
A Mishra, D Marr
arXiv preprint arXiv:1711.05852, 2017
3932017
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
A Jog, O Kayiran, N Chidambaram Nachiappan, AK Mishra, MT Kandemir, ...
ACM SIGPLAN Notices 48 (4), 395-406, 2013
3882013
WRPN: Wide reduced-precision networks
A Mishra, E Nurvitadhi, JJ Cook, D Marr
arXiv preprint arXiv:1709.01134, 2017
3792017
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
A Jog, AK Mishra, C Xu, Y Xie, V Narayanan, R Iyer, CR Das
Proceedings of the 49th Annual Design Automation Conference, 243-252, 2012
3582012
MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
ACM SIGARCH Computer Architecture News 36 (3), 251-261, 2008
3022008
Orchestrated scheduling and prefetching for GPGPUs
A Jog, O Kayiran, AK Mishra, MT Kandemir, O Mutlu, R Iyer, CR Das
Proceedings of the 40th Annual International Symposium on Computer …, 2013
2592013
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
R Das, S Eachempati, AK Mishra, V Narayanan, CR Das
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
2562009
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC
E Nurvitadhi, J Sim, D Sheffield, A Mishra, S Krishnan, D Marr
2016 26th International Conference on Field Programmable Logic and …, 2016
2482016
Scheduling techniques for GPU architectures with processing-in-memory capabilities
A Pattnaik, X Tang, A Jog, O Kayiran, AK Mishra, MT Kandemir, O Mutlu, ...
Proceedings of the 2016 International Conference on Parallel Architectures …, 2016
2472016
Accelerating sparse deep neural networks
A Mishra, JA Latorre, J Pool, D Stosic, D Stosic, G Venkatesh, C Yu, ...
arXiv preprint arXiv:2104.08378, 2021
2342021
A case for heterogeneous on-chip interconnects for CMPs
AK Mishra, N Vijaykrishnan, CR Das
ACM SIGARCH Computer Architecture News 39 (3), 389-400, 2011
1562011
A case for dynamic frequency tuning in on-chip networks
AK Mishra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, CR Das
Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009
1502009
Runnemede: An architecture for ubiquitous high-performance computing
NP Carter, A Agrawal, S Borkar, R Cledat, H David, D Dunning, J Fryman, ...
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
1392013
Performance and power optimization through data compression in network-on-chip architectures
R Das, AK Mishra, C Nicopoulos, D Park, V Narayanan, R Iyer, MS Yousif, ...
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
1352008
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
AK Mishra, X Dong, G Sun, Y Xie, N Vijaykrishnan, CR Das
ACM SIGARCH Computer Architecture News 39 (3), 69-80, 2011
1342011
A customizable matrix multiplication framework for the intel harpv2 xeon+ fpga platform: A deep learning case study
DJM Moss, S Krishnan, E Nurvitadhi, P Ratuszniak, C Johnson, J Sim, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
1072018
A heterogeneous multiple network-on-chip design: an application-aware approach
AK Mishra, O Mutlu, CR Das
Proceedings of the 50th annual design automation conference, 1-10, 2013
1072013
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Artikkelit 1–20