Seuraa
Jacob Leverich
Jacob Leverich
PhD in Computer Science, Stanford University
Vahvistettu sähköpostiosoite verkkotunnuksessa cs.stanford.edu - Kotisivu
Nimike
Viittaukset
Viittaukset
Vuosi
The case for RAMClouds: scalable high-performance storage entirely in DRAM
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazières, ...
ACM SIGOPS Operating Systems Review 43 (4), 92-105, 2010
7452010
On the energy (in) efficiency of hadoop clusters
J Leverich, C Kozyrakis
ACM SIGOPS Operating Systems Review 44 (1), 61-65, 2010
5292010
Reconciling high server utilization and sub-millisecond quality-of-service
J Leverich, C Kozyrakis
Proceedings of the Ninth European Conference on Computer Systems, 1-14, 2014
2852014
The case for RAMCloud
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazières, ...
Communications of the ACM 54 (7), 121-130, 2011
2372011
Power management of datacenter workloads using per-core power gating
J Leverich, M Monchiero, V Talwar, P Ranganathan, C Kozyrakis
IEEE Computer Architecture Letters 8 (2), 48-51, 2009
1762009
Comparing memory systems for chip multiprocessors
J Leverich, H Arakida, A Solomatnikov, A Firoozshahian, M Horowitz, ...
ACM SIGARCH Computer Architecture News 35 (2), 358-368, 2007
1532007
Future scaling of processor-memory interfaces
JH Ahn, NP Jouppi, C Kozyrakis, J Leverich, RS Schreiber
Proceedings of the Conference on High Performance Computing Networking …, 2009
1412009
Multicore DIMM: An energy efficient memory module with independently controlled DRAMs
JH Ahn, J Leverich, R Schreiber, NP Jouppi
IEEE Computer Architecture Letters 8 (1), 5-8, 2008
1262008
Improving system energy efficiency with memory rank subsetting
JH Ahn, NP Jouppi, C Kozyrakis, J Leverich, RS Schreiber
ACM Transactions on Architecture and Code Optimization (TACO) 9 (1), 1-28, 2012
442012
Independently controlled virtual memory devices in memory modules
JH Ahn, NP Jouppi, JB Leverich
US Patent 8,788,747, 2014
282014
Comparative evaluation of memory models for chip multiprocessors
J Leverich, H Arakida, A Solomatnikov, A Firoozshahian, M Horowitz, ...
ACM Transactions on Architecture and Code Optimization (TACO) 5 (3), 1-30, 2008
182008
Integrated circuit package
M Monchiero, JB Leverich, P Ranganathan, NP Jouppi, V Talwar
US Patent 8,907,462, 2014
152014
Dynamic utilization of power-down modes in multi-core memory modules
JH Ahn, NP Jouppi, JB Leverich, RS Schreiber
US Patent 8,812,886, 2014
152014
Future scaling of datacenter power-efficiency
JB Leverich
Stanford University, 2014
122014
Evaluating impact of manageability features on device performance
J Leverich, V Talwar, P Ranganathan, C Kozyrakis
2010 International Conference on Network and Service Management, 426-430, 2010
22010
Eric Stratmann The case for RAMClouds: scalable high-performance storage entirely in DRAM In
JK Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazires, ...
Operating Systems Review-SIGOPS, 92-105, 0
2
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Artikkelit 1–16