| A novel architecture for real time implementation of edge detectors on FPGA KC Sudeep, J Majumdar International Journal of Computer Science Issues (IJCSI) 8 (1), 193, 2011 | 46 | 2011 |
| Execution of dataflow process networks on OpenCL platforms W Lund, S Kanur, J Ersfolk, L Tsiopoulos, J Lilius, J Haldin, U Falk 2015 23rd Euromicro International Conference on Parallel, Distributed, and …, 2015 | 28 | 2015 |
| Task-based execution of synchronous dataflow graphs for scalable multicore computing G Georgakarakos, S Kanur, J Lilius, K Desnos 2017 IEEE International Workshop on Signal Processing Systems (SiPS), 1-6, 2017 | 4 | 2017 |
| Detecting data-parallel synchronous dataflow graphs S Kanur, J Lilius, J Ersfolk 2017 Conference on Design and Architectures for Signal and Image Processing …, 2017 | 1 | 2017 |
| Determining a device crossover point in CPU/GPU systems for streaming applications S Kanur, W Lund, L Tsiopoulos, J Lilius 2015 IEEE Global Conference on Signal and Information Processing (GlobalSIP …, 2015 | 1 | 2015 |
| ARCHITECTURE DESIGN AND EVALUATION OF LDPC DECODER ON TTA BASED CODESIGN ENVIRONMENT SKC Shekar | | 2013 |
| Parallel decoder for low density parity check codes: A MPSoC study S Kanur, G Georgakarakos, A Simlä, J Lagravière, K Nybom, S Lafond, ... 2013 International Conference on High Performance Computing & Simulation …, 2013 | | 2013 |
| DECODING OF DVB-T2 LDPC CODES ON A TILE PROCESSOR: OPTIMISATIONS AND PERFORMANCE COMPARISONS S Kanur, S Grönroos, K Nybom, J Björkqvist, J Lilius | | |
