Jingsheng Jason Cong
Jingsheng Jason Cong
Chancellor's Professor of Computer Science and Electrical Engineering, University of California, Los
Verified email at cs.ucla.edu - Homepage
Title
Cited by
Cited by
Year
Optimizing fpga-based accelerator design for deep convolutional neural networks
C Zhang, P Li, G Sun, Y Guan, B Xiao, J Cong
Proceedings of the 2015 ACM/SIGDA international symposium on field …, 2015
12112015
FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
J Cong, Y Ding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1994
849*1994
High-level synthesis for FPGAs: From prototyping to deployment
J Cong, B Liu, S Neuendorffer, J Noguera, K Vissers, Z Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
6612011
High-Level Synthesis for FPGAs: From Prototyping to Deployment
Cong
661*
A thermal-driven floorplanning algorithm for 3D ICs
J Cong, J Wei, Y Zhang
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
4882004
Performance optimization of VLSI interconnect layout
J Cong, L He, CK Koh, PH Madden
Integration 21 (1-2), 1-94, 1996
3821996
CMP network-on-chip overlaid with multi-band RF-interconnect
MF Chang, J Cong, A Kaplan, M Naik, G Reinman, E Socher, SW Tam
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
3032008
Application-specific instruction generation for configurable processor architectures
J Cong, Y Fan, G Han, Z Zhang
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field …, 2004
2892004
Combinational logic synthesis for LUT based field programmable gate arrays
J Cong, Y Ding
ACM Transactions on Design Automation of Electronic Systems (TODAES) 1 (2 …, 1996
2751996
Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks
C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
2732018
An interconnect-centric design flow for nanometer technologies
J Cong
Proceedings of the IEEE 89 (4), 505-528, 2001
2612001
On area/depth trade-off in LUT-based FPGA technology mapping
J Cong, Y Ding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2), 137-148, 1994
2511994
Provably good performance-driven global routing
J Cong, AB Kahng, G Robins, M Sarrafzadeh, CK Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992
2431992
Interconnect design for deep submicron ICs
Z Pan, L He, CK Koh, KY Khoo
1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997
2411997
Performance-driven interconnect design based on distributed RC delay model
J Cong, KS Leung, D Zhou
30th ACM/IEEE Design Automation Conference, 606-611, 1993
2281993
mPL6: enhanced multilevel mixed-size placement
TF Chan, J Cong, JR Shinnerl, K Sze, M Xie
Proceedings of the 2006 international symposium on Physical design, 212-214, 2006
2252006
Minimizing computation in convolutional neural networks
J Cong, B Xiao
International conference on artificial neural networks, 281-290, 2014
2222014
A scalable micro wireless interconnect structure for CMPs
SB Lee, SW Tam, I Pefkianakis, S Lu, MF Chang, C Guo, G Reinman, ...
Proceedings of the 15th annual international conference on Mobile computing …, 2009
2222009
Architecture evaluation for power-efficient FPGAs
F Li, D Chen, L He, J Cong
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003
2222003
Multilevel generalized force-directed method for circuit placement
T Chan, J Cong, K Sze
Proceedings of the 2005 international symposium on Physical design, 185-192, 2005
2212005
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Articles 1–20