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Nazanin Mansouri
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Reliability-centric high-level synthesis
S Tosun, N Mansouri, E Arvas, M Kandemir, Y Xie
Design, Automation and Test in Europe, 1258-1263, 2005
972005
An ILP formulation for reliability-oriented high-level synthesis
S Tosun, O Ozturk, N Mansouri, E Arvas, M Kandemir, Y Xie, WL Hung
Sixth international symposium on quality electronic design (isqed'05), 364-369, 2005
482005
Automated formal verification of scheduling process using finite state machines with datapath (fsmd)
Y Kim, S Kopuri, N Mansouri
Quality Electronic Design, 2004. Proceedings. 5th International Symposium on …, 2004
392004
Reliability-centric hardware/software co-design
S Tosun, N Mansouri, E Arvas, M Kandemir, Y Xie, WL Hung
Sixth international symposium on quality electronic design (isqed'05), 375-380, 2005
382005
A methodology for automated verification of synthesized rtl designs and its integration with a high-level synthesis tool
N Mansouri, R Vemuri
International Conference on Formal Methods in Computer-Aided Design, 204-221, 1998
261998
Automatic data path abstraction for verification of large scale designs
V Paruthi, N Mansouri, R Vemuri
Computer Design: VLSI in Computers and Processors, 1998. ICCD'98 …, 1998
261998
Automated formal verification of scheduling with speculative code motions
Y Kim, N Mansouri
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 95-100, 2008
212008
Power islands: a high-level technique for counteracting leakage in deep sub-micron
D Dal, A Nunez, N Mansouri
Proceedings of the 7th International Symposium on Quality Electronic Design …, 2006
212006
Power optimization with power islands synthesis
D Dal, N Mansouri
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
192009
An ILP formulation for task scheduling on heterogeneous chip multiprocessors
S Tosun, N Mansouri, M Kandemir, O Ozturk
International Symposium on Computer and Information Sciences, 267-276, 2006
142006
Enhancing scheduling solutions through ant colony optimization
S Kopuri, N Mansouri
Circuits and Systems, 2004. ISCAS'04. Proceedings of the 2004 International …, 2004
142004
Automated correctness condition generation for formal verification of synthesized RTL designs
N Mansouri, R Vemuri
Formal Methods in System Design 16 (1), 59-91, 2000
142000
Power islands: A high-level synthesis technique for reducing spurious switching activity and leakage
D Dal, D Kutagulla, A Nunez, N Mansouri
48th Midwest Symposium on Circuits and Systems, 2005., 1875-1879, 2005
122005
A high-level register optimization technique for minimizing leakage and dynamic power
D Dal, N Mansouri
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 517-520, 2007
82007
PROVERIFIC: experiments in employing (PSL) standard assertions in theorem-proving-based verification
P Sule, Y Kim, N Mansouri
48th Midwest Symposium on Circuits and Systems, 2005., 112-115, 2005
72005
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
N Mansouri, R Vemuri
Proceedings of the conference on Design, automation and test in Europe, 46, 1999
71999
Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits
S Shah, N Mansouri, A Nunez-Aldana
16th International Conference on Electronics, Communications and Computers …, 2006
42006
Interconnect-centric high level synthesis for enhanced layouts with reduced wire length
P Parakh, D Mullassery, A Chandrashekar, H Koc, D Dal, N Mansouri
2006 49th IEEE International Midwest Symposium on Circuits and Systems 2 …, 2006
32006
Constraint-based Code mapping for heterogeneous Chip multiprocessors
S Tosun, N Mansouri, M Kandemir, O Ozturk
Proceedings 2005 IEEE International SOC Conference, 89-90, 2005
32005
Determining the optimal number of islands in power islands synthesis
D Dal, N Mansouri
2008 IEEE Computer Society Annual Symposium on VLSI, 22-27, 2008
22008
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