Seuraa
Jue Wang
Jue Wang
Ph.D. of Computer Science & Engineering, PSU
Vahvistettu sähköpostiosoite verkkotunnuksessa cse.psu.edu
Nimike
Viittaukset
Viittaukset
Vuosi
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations
J Wang, X Dong, Y Xie, NP Jouppi
2013 IEEE 19th international symposium on high performance computer …, 2013
1562013
OAP: An obstruction-aware cache management policy for STT-RAM last-level caches
J Wang, X Dong, Y Xie
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 847-852, 2013
842013
Energy-efficient multi-level cell phase-change memory system with data encoding
J Wang, X Dong, G Sun, D Niu, Y Xie
2011 IEEE 29th International Conference on Computer Design (ICCD), 175-182, 2011
792011
A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications
J Wang, Y Liu, H Yang, H Wang
The 2010 International Conference on Green Circuits and Systems, 646-650, 2010
552010
Enabling high-performance LPDDRx-compatible MRAM
J Wang, X Dong, Y Xie
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
332014
ProactiveDRAM: A DRAM-initiated retention management scheme
J Wang, X Dong, Y Xie
2014 IEEE 32nd International Conference on Computer Design (ICCD), 22-27, 2014
292014
Endurance-aware cache line management for non-volatile caches
J Wang, X Dong, Y Xie, NP Jouppi
ACM Transactions on Architecture and Code Optimization (TACO) 11 (1), 1-25, 2014
292014
Point and discard: a hard-error-tolerant architecture for non-volatile last level caches
J Wang, X Dong, Y Xie
Proceedings of the 49th Annual Design Automation Conference, 253-258, 2012
262012
A write-aware STTRAM-based register file architecture for GPGPU
J Wang, Y Xie
ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (1), 1-12, 2015
232015
Building and optimizing MRAM-based commodity memories
J Wang, X Dong, Y Xie
ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-22, 2014
112014
Energy efficient architecture of sensor network node based on compression accelerator
J Wang, B Ying, Y Liu, H Yang, H Wang
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 117-120, 2009
52009
Preventing STT-RAM last-level caches from port obstruction
J Wang, X Dong, Y Xie
ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-19, 2014
42014
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Artikkelit 1–12