Peichen Pan
Peichen Pan
Unknown affiliation
Verified email at falcon-computing.com
TitleCited byYear
Caffeine: Toward uniformed representation and acceleration for deep convolutional neural networks
C Zhang, G Sun, Z Fang, P Zhou, P Pan, J Cong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
2262018
FPGA design automation: A survey
D Chen, J Cong, P Pan
Foundations and Trends® in Electronic Design Automation 1 (3), 195-330, 2006
2002006
A new retiming-based technology mapping algorithm for LUT-based FPGAs
P Pan, CC Lin
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field …, 1998
981998
Optimal clock period clustering for sequential circuits with retiming
P Pan, AK Karandikar, CL Liu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
551998
Area minimization for floorplans
P Pan, CL Liu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
521995
Optimal clock period FPGA technology mapping for sequential circuits
P Pan, CL Liu
ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (3 …, 1998
471998
Continuous retiming: Algorithms and applications
P Pan
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
321997
Area minimization for hierarchical floorplans
P Pan, W Shi, CL Liu
Algorithmica 15 (6), 550-571, 1996
291996
Performance-driven integration of retiming and resynthesis
P Pan
Proceedings of the 36th annual ACM/IEEE design automation conference, 243-246, 1999
251999
Source-to-source optimization for HLS
J Cong, M Huang, P Pan, Y Wang, P Zhang
FPGAs for Software Programmers, 137-163, 2016
202016
Area minimization for general floorplans
P Pan, CL Liu
IEEE International Conference on Computer Aided Design, 606-606, 1992
151992
Optimal retiming for initial state computation
P Pan, G Chen
Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999
121999
Software infrastructure for enabling FPGA-based accelerations in data centers
J Cong, M Huang, P Pan, D Wu, P Zhang
Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016
112016
Monotone bipartitioning problem in a planar point set with applications to VLSI
P Dasgupta, P Pan, SC Nandy, BB Bhattacharya
ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (2 …, 2002
112002
Optimal graph constraint reduction for symbolic layout compaction
P Pan, SK Dong, CL Liu
Proceedings of the 30th international Design Automation Conference, 401-406, 1993
111993
Technology mapping of sequential circuits for LUT-based FPGAs for performance
P Pan, CL Liu
Proceedings of the 1996 ACM fourth international symposium on Field …, 1996
101996
Partial scan with pre-selected scan signals
CLLP Pan
32nd Design Automation Conference, 189-194, 1995
9*1995
Partial scan with pre-selected scan signals
CLLP Pan
32nd Design Automation Conference, 189-194, 1995
81995
The retiming of single-phase clocked circuits containing level-sensitive latches
P Saxena, P Pan, CL Liu
Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999
41999
Optimal clock period clustering for sequential circuits with retiming
AK Karandikar, P Pan, CL Liu
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
21997
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Articles 1–20