| Sequoia: Programming the memory hierarchy K Fatahalian, DR Horn, TJ Knight, L Leem, M Houston, JY Park, M Erez, ... Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, 83-es, 2006 | 685 | 2006 |
| Addressing failures in exascale computing M Snir, RW Wisniewski, JA Abraham, SV Adve, S Bagchi, P Balaji, J Belak, ... The International Journal of High Performance Computing Applications 28 (2 …, 2014 | 528 | 2014 |
| Merrimac: Supercomputing with streams WJ Dally, F Labonte, A Das, P Hanrahan, JH Ahn, J Gummaraju, M Erez, ... Proceedings of the 2003 ACM/IEEE Conference on Supercomputing, 35, 2003 | 459 | 2003 |
| FREE-p: Protecting non-volatile memory against both hard and soft errors DH Yoon, N Muralimanohar, J Chang, P Ranganathan, NP Jouppi, ... 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 252 | 2011 |
| Speculation techniques for improving load related instruction scheduling A Yoaz, M Erez, R Ronen, S Jourdan Proceedings of the 26th annual international symposium on Computer …, 1999 | 238 | 1999 |
| Virtualized and flexible ECC for main memory DH Yoon, M Erez Proceedings of the fifteenth International Conference on Architectural …, 2010 | 193 | 2010 |
| Balancing DRAM locality and parallelism in shared memory CMP systems MK Jeong, DH Yoon, D Sunwoo, M Sullivan, I Lee, M Erez IEEE International symposium on high-performance comp architecture, 1-12, 2012 | 181 | 2012 |
| Memory mapped ECC: Low-cost error protection for last level caches DH Yoon, M Erez Proceedings of the 36th annual international symposium on Computer …, 2009 | 177 | 2009 |
| A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC MK Jeong, M Erez, C Sudanthi, N Paver Proceedings of the 49th Annual Design Automation Conference, 850-855, 2012 | 172 | 2012 |
| Dirigent: Enforcing QoS for latency-critical tasks on shared multicore systems H Zhu, M Erez Proceedings of the twenty-first international conference on architectural …, 2016 | 169 | 2016 |
| A locality-aware memory hierarchy for energy-efficient GPU architectures M Rhu, M Sullivan, J Leng, M Erez Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 168 | 2013 |
| Containment domains: A scalable, efficient and flexible resilience scheme for exascale systems J Chung, I Lee, M Sullivan, JH Ryoo, DW Kim, DH Yoon, L Kaplan, M Erez Scientific Programming 21 (3-4), 197-212, 2013 | 134 | 2013 |
| Adaptive granularity memory systems: A tradeoff between storage efficiency and throughput DH Yoon, MK Jeong, M Erez Proceedings of the 38th annual international symposium on Computer …, 2011 | 134 | 2011 |
| Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory J Kim, M Sullivan, M Erez 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 130 | 2015 |
| NBTI-aware DVFS: A new approach to saving energy and increasing processor lifetime M Basoglu, M Orshansky, M Erez Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 130 | 2010 |
| Compilation for explicitly managed memory hierarchies TJ Knight, JY Park, M Ren, M Houston, M Erez, K Fatahalian, A Aiken, ... Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of …, 2007 | 120 | 2007 |
| Priority-based cache allocation in throughput processors D Li, M Rhu, DR Johnson, M O'Connor, M Erez, D Burger, DS Fussell, ... 2015 IEEE 21st International Symposium on High Performance Computer …, 2015 | 117 | 2015 |
| Bit-plane compression: Transforming data for better compression in many-core architectures J Kim, M Sullivan, E Choukse, M Erez ACM SIGARCH Computer Architecture News 44 (3), 329-340, 2016 | 111 | 2016 |
| Hemem: Scalable tiered memory management for big data applications and real nvm A Raybuck, T Stamler, W Zhang, M Erez, S Peter Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles …, 2021 | 109 | 2021 |
| NoC with near-ideal express virtual channels using global-line communication T Krishna, A Kumar, P Chiang, M Erez, LS Peh 2008 16th IEEE Symposium on High Performance Interconnects, 11-20, 2008 | 99 | 2008 |
William DallyChief Scientist, NVIDIA; Adjunct Professor of CS and EE, Stanford University;Verified email at stanford.edu
