| Self-organizing multiple appliance network connectivity apparatus for controlling plurality of appliances MA Indovina, JM Indovina, RD Priebe, CA Barrios, SL Boggs US Patent 9,197,949, 2015 | 38 | 2015 |
| The advances, challenges and future possibilities of millimeter-wave chip-to-chip interconnections for multi-chip systems A Ganguly, MM Ahmed, R Singh Narde, A Vashist, MS Shamim, ... Journal of Low Power Electronics and Applications 8 (1), 5, 2018 | 36 | 2018 |
| Industrially proving the SPIRIT consortium specifications for design chain integration P Bricaud, F Remond, O Florent, J Wilson, M Strik, C Ussery, M Indovina, ... Proceedings of the Design Automation & Test in Europe Conference 2, 1-6, 2006 | 34 | 2006 |
| pPIM: A programmable processor-in-memory architecture with precision-scaling for deep learning PR Sutradhar, M Connolly, S Bavikadi, SMP Dinakarrao, MA Indovina, ... IEEE Computer Architecture Letters 19 (2), 118-121, 2020 | 33 | 2020 |
| Look-up-table based processing-in-memory architecture with programmable precision-scaling for deep learning applications PR Sutradhar, S Bavikadi, M Connolly, S Prajapati, MA Indovina, ... IEEE Transactions on Parallel and Distributed Systems 33 (2), 263-275, 2021 | 25 | 2021 |
| Designer configurable multi-processor system C Ussery, O Levia, J Gostomski, G Derti, M Indovina US Patent App. 09/757,373, 2001 | 20 | 2001 |
| A 0.36 pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects S Subramaniam, T Shinde, P Deshmukh, MS Shamim, M Indovina, ... 2017 30th IEEE International System-on-Chip Conference (SOCC), 132-137, 2017 | 18 | 2017 |
| A 0.24 pJ/bit, 16Gbps OOK transmitter circuit in 45-nm CMOS for inter and intra-chip wireless interconnects T Shinde, S Subramaniam, P Deshmukh, MM Ahmed, M Indovina, ... Proceedings of the 2018 on Great Lakes Symposium on VLSI, 69-74, 2018 | 13 | 2018 |
| A Top-Down approach to IC design C Browy, G Gullikson, M Indovina Integrated Circuit Design Methodology Guide 2000, 1997 | 10 | 1997 |
| Implementation and evaluation of deep neural networks in commercially available processing in memory hardware P Das, PR Sutradhar, M Indovina, SMP Dinakarrao, A Ganguly 2022 IEEE 35th International System-on-Chip Conference (SOCC), 1-6, 2022 | 5 | 2022 |
| Polar: Performance-aware on-device learning capable programmable processing-in-memory architecture for low-power ml applications S Bavikadi, PR Sutradhar, MA Indovina, A Ganguly, SMP Dinakarrao 2022 25th Euromicro Conference on Digital System Design (DSD), 889-898, 2022 | 5 | 2022 |
| Digital neuromorphic chips for deep learning inference: a comprehensive study HF Langroudi, T Pandit, M Indovina, D Kudithipudi Proc. SPIE 11139, Applications of Machine Learning, 111390, 2018 | 4 | 2018 |
| Testing winoc-enabled multicore chips with bist for wireless interconnects A Vashist, A Ganguly, M Indovina 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2018 | 3 | 2018 |
| 3DL-PIM: A Look-up Table oriented Programmable Processing in Memory Architecture based on the 3-D Stacked Memory for Data-Intensive Applications PR Sutradhar, S Bavikadi, SMP Dinakarrao, MA Indovina, A Ganguly IEEE Transactions on Emerging Topics in Computing, 2023 | 2 | 2023 |
| FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications PR Sutradhar, S Bavikadi, M Indovina, SM Pudukotai Dinakarrao, ... Proceedings of the Great Lakes Symposium on VLSI 2023, 207-211, 2023 | 2 | 2023 |
| Flexible instruction set architecture for programmable look-up table based processing-in-memory M Connolly, PR Sutradhar, M Indovina, A Ganguly 2021 IEEE 39th International Conference on Computer Design (ICCD), 66-73, 2021 | 1 | 2021 |
| Self-organized multiple appliance network connectivity apparatus MA Indovina, JM Indovina, RD Priebe, CA Barrios, SL Boggs US Patent 10,462,022, 2019 | 1 | 2019 |
| Self-organized multiple appliance network connectivity apparatus MA Indovina, JM Indovina, RD Priebe, CA Barrios, SL Boggs US Patent 9,438,492, 2016 | 1 | 2016 |
| ReApprox-PIM: Reconfigurable Approximate Look-Up-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator S Bavikadi, PR Sutradhar, M Indovina, A Ganguly, SMP Dinakarrao IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Look-up Table Containing Processor-in-memory Cluster For Data-intensive Applications A Ganguly, SMP Dinakarrao, M Connolly, PR Sutradhar, S Bavikadi, ... US Patent 11,775,312, 2023 | | 2023 |
Amlan GangulyDepartment Head and Professor of Computer Engineering, Rochester Institute of TechnologyVerified email at rit.edu
