| Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor M Si, C Jiang, W Chung, Y Du, MA Alam, PD Ye Nano Letters 18 (6), 3682-3687, 2018 | 119 | 2018 |
| Sub-60 mV/dec ferroelectric HZO MoS2negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance M Si, C Jiang, CJ Su, YT Tang, L Yang, W Chung, MA Alam, PD Ye 2017 IEEE International Electron Devices Meeting (IEDM), 23.5. 1-23.5. 4, 2017 | 62 | 2017 |
| Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec W Chung, M Si, PD Ye Electron Devices Meeting (IEDM), 2017 IEEE International, 15.3. 1-15.3. 4, 2017 | 62 | 2017 |
| First demonstration of Ge ferroelectric nanowire FET as synaptic device for online learning in neural network with high number of conductance state and G max/G min W Chung, M Si, DY Peide 2018 IEEE International Electron Devices Meeting (IEDM), 15.2. 1-15.2. 4, 2018 | 52 | 2018 |
| Solar-Blind UV Photodetector Based on Atomic Layer-Deposited Cu2O and Nanomembrane β-Ga2O3 pn Oxide Heterojunction H Bae, A Charnas, X Sun, J Noh, M Si, W Chung, G Qiu, X Lyu, ... ACS omega 4 (24), 20756-20761, 2019 | 35 | 2019 |
| First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric … W Chung, M Si, PR Shrestha, JP Campbell, KP Cheung, DY Peide 2018 IEEE Symposium on VLSI Technology, 89-90, 2018 | 32 | 2018 |
| A novel scalable energy-efficient synaptic device: Crossbar ferroelectric semiconductor junction M Si, Y Luo, W Chung, H Bae, D Zheng, J Li, J Qin, G Qiu, S Yu, PD Ye 2019 IEEE International Electron Devices Meeting (IEDM), 6.6. 1-6.6. 4, 2019 | 27 | 2019 |
| First experimental demonstration of robust HZO/β-Ga₂O₃ ferroelectric field-effect transistors as synaptic devices for artificial intelligence applications in a high … J Noh, H Bae, J Li, Y Luo, Y Qu, TJ Park, M Si, X Chen, AR Charnas, ... IEEE Transactions on Electron Devices 68 (5), 2515-2521, 2021 | 17 | 2021 |
| Performance potential of Ge CMOS technology from a material-device-circuit perspective SH Shin, H Jiang, W Ahn, H Wu, W Chung, DY Peide, MA Alam IEEE Transactions on Electron Devices 65 (5), 1679-1684, 2018 | 17 | 2018 |
| First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors H Bae, TJ Park, J Noh, W Chung, M Si, S Ramanathan, DY Peide Nanotechnology 33 (12), 125201, 2021 | 12 | 2021 |
| Demonstration of Ge pMOSFETs with 6 Å EOT using TaN/ZrO2/Zr-cap/n-Ge(100) gate stack fabricated by novel vacuum annealing and in-situ metal capping method Y Shin, W Chung, Y Seo, CH Lee, DK Sohn, BJ Cho 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 12 | 2014 |
| The impact of channel semiconductor on the memory characteristics of ferroelectric field-effect transistors M Si, Z Lin, J Noh, J Li, W Chung, DY Peide IEEE Journal of the Electron Devices Society 8, 846-849, 2020 | 10 | 2020 |
| Controlling threshold voltage of CMOS SOI nanowire FETs with sub-1 nm dipole layers formed by atomic layer deposition D Zheng, W Chung, Z Chen, M Si, C Wilk, DY Peide IEEE Transactions on Electron Devices 69 (2), 851-856, 2021 | 5 | 2021 |
| Experimental extraction of ballisticity in germanium nanowire nMOSFETs W Chung, H Wu, W Wu, M Si, DY Peide IEEE Transactions on Electron Devices 66 (8), 3541-3548, 2019 | 5 | 2019 |
| Alleviation of short channel effects in Ge negative capacitance pFinFETs W Chung, M Si, DY Peide 2018 76th Device Research Conference (DRC), 1-2, 2018 | 5 | 2018 |
| Ultrathin transparent Copper (I) oxide films grown by plasma-enhanced atomic layer deposition for Back-end-of-line p-Type transistors H Bae, A Charnas, W Chung, M Si, X Lyu, X Sun, J Park, H Wang, ... Nano Express 2 (2), 020023, 2021 | 4 | 2021 |
| Integration of ALD high-k dipole layers into CMOS SOI nanowire FETs for bi-directional threshold voltage engineering W Chung, D Zheng, WE Wang, M Rodder, DY Peide 2020 IEEE Silicon Nanoelectronics Workshop (SNW), 15-16, 2020 | 1 | 2020 |
| Integration of ferroelectricity into advanced 3D germanium MOSFETs for memory and logic applications W Chung Purdue University, 2019 | 1 | 2019 |
| Time response of polarization switching in Ge hafnium zirconium oxide nanowire ferroelectric field-effect transistors S Alghamdi, W Chung, M Si, DY Peide 2018 76th Device Research Conference (DRC), 1-2, 2018 | 1 | 2018 |
| Integration of Germanium into Modern CMOS: Challenges and Breakthroughs W Chung, H Wu, PD Ye Advanced Nanoelectronics: Post‐Silicon Materials and Devices, 91-117, 2018 | | 2018 |
Peide YeRichard J. and Mary Jo Schwartz Professor of Electrical and Computer Engineering, Purdue UniversityVahvistettu sähköpostiosoite verkkotunnuksessa purdue.edu
