| Maskednet: The first hardware inference engine aiming power side-channel protection A Dubey, R Cammarota, A Aysu 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 68 | 2020 |
| BoMaNet: Boolean masking of an entire neural network A Dubey, R Cammarota, A Aysu Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 43 | 2020 |
| Maskednet: A pathway for secure inference against power side-channel attacks A Dubey, R Cammarota, A Aysu arXiv preprint arXiv:1910.13063 7, 21-39, 2019 | 21 | 2019 |
| Guarding machine learning hardware against physical side-channel attacks A Dubey, R Cammarota, V Suresh, A Aysu ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (3), 1-31, 2022 | 20 | 2022 |
| Modulonet: Neural networks meet modular arithmetic for efficient hardware masking A Dubey, A Ahmad, MA Pasha, R Cammarota, A Aysu IACR Transactions on Cryptographic Hardware and Embedded Systems, 506-556, 2022 | 16 | 2022 |
| Trustworthy AI inference systems: An industry research view R Cammarota, M Schunter, A Rajan, F Boemer, Á Kiss, A Treiber, ... arXiv preprint arXiv:2008.04449, 2020 | 11 | 2020 |
| Hardware-software co-design for side-channel protected neural network inference A Dubey, R Cammarota, A Varna, R Kumar, A Aysu 2023 IEEE International Symposium on Hardware Oriented Security and Trust …, 2023 | 5 | 2023 |
| High-fidelity model extraction attacks via remote power monitors A Dubey, E Karabulut, A Awad, A Aysu 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 5 | 2022 |
| Hands-on teaching of hardware security for machine learning A Calhoun, E Ortega, F Yaman, A Dubey, A Aysu Proceedings of the Great Lakes Symposium on VLSI 2022, 455-461, 2022 | 4 | 2022 |
| Comparative Study of CHStone Benchmarks on Xilinx Vivado High Level Synthesis Tool A Dubey, A Mishra, S Bhutada International Journal of Engineering Research & Technology 4 (1), 237-242, 2015 | 2 | 2015 |
| Maskednet: a pathway for secure inference against power side-channel attacks. CoRR abs/1910.13063 (2019) A Dubey, R Cammarota, A Aysu | 2 | 1910 |
| Design of ultra low power flip flops in sub-threshold region for bio-medical application in 45nm, 32nm and 22nm technologies S Bhutada, A Asati, A Dubey 2015 IEEE International Conference on Electrical, Computer and Communication …, 2015 | 1 | 2015 |
| A Full-Stack Approach for Side-Channel Secure ML Hardware A Dubey, A Aysu 2023 IEEE International Test Conference (ITC), 186-195, 2023 | | 2023 |
| A (Cont.) A Dubey, A Lele, A Aysu, BP Duisterhof, B Yu, BX Wu, B Li, BG Taylor, ... | | |
| Journal: Proceedings of the 39th International Conference on Computer-Aided Design, 2020 A Dubey, R Cammarota, A Aysu | | |
Aydin AysuNorth Carolina State UniversityVahvistettu sähköpostiosoite verkkotunnuksessa vt.edu
