Tsutomu Sasao
Tsutomu Sasao
Visiting Professor, Meiji University
Verified email at cs.meiji.ac.jp - Homepage
Title
Cited by
Cited by
Year
Switching theory for logic synthesis
T Sasao
Springer Science & Business Media, 2012
5272012
Representations of discrete functions
T Sasao, M Fujita
Springer US, 1996
3491996
Logic synthesis and optimization
T Sasao
Kluwer Academic Publishers, 1993
3391993
On the complexity of mod-2l sum PLA's
T Sasao, P Besslich
IEEE Transactions on Computers 39 (2), 262-266, 1990
2641990
EXMIN2: A simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
T Sasao
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
2001993
Logic synthesis and verification
S Hassoun, T Sasao
Springer Science & Business Media, 2012
1972012
Input variable assignment and output phase optimization of PLA's
T Sasao
IEEE Computer Architecture Letters 33 (10), 879-894, 1984
1921984
FPGA design by generalized functional decomposition
T Sasao
Logic synthesis and optimization, 233-258, 1993
1381993
Easily testable realizations for generalized Reed-Muller expressions
T Sasao
IEEE transactions on computers 46 (6), 709-716, 1997
1151997
Multiple-valued decomposition of generalized Boolean functions and the complexity of programmable logic arrays
T Sasao
IEEE Computer Architecture Letters 30 (09), 635-643, 1981
1141981
AND-EXOR expressions and their optimization
T Sasao
Logic synthesis and optimization, 287-312, 1993
1071993
Memory-based logic synthesis
T Sasao
Springer Science & Business Media, 2011
962011
On the optimal design of multiple-valued PLAs
T Sasao
IEEE transactions on computers 38 (4), 582-592, 1989
961989
A method to represent multiple-output switching functions by using multi-valued decision diagrams
T Sasao, JT Butler
Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic …, 1996
931996
Representations of logic functions using EXOR operators
T Sasao
Representations of discrete functions, 29-54, 1996
921996
A cascade realization of multiple-output function for reconfigurable hardware
T Sasao, M Matsuura, Y Iguchi
International Workshop on Logic and Synthesis (IWLS01), 12-15, 2001
892001
Numerical function generators using LUT cascades
T Sasao, S Nagayama, JT Butler
IEEE Transactions on Computers 56 (6), 826-838, 2007
792007
Selection of potentially testable path delay faults for test generation
A Murakami, S Kajihara, T Sasao, I Pomeranz, SM Reddy
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
782000
Ternary decision diagrams. Survey
T Sasao
Proceedings 1997 27th International Symposium on Multiple-Valued Logic, 241-250, 1997
771997
Minimization of AND-EXOR expressions using rewrite rules
D Brand, T Sasao
IEEE Transactions on Computers 42 (5), 568-576, 1993
731993
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