The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 122 | 2018 |
Blackparrot: An agile open-source risc-v multicore for accelerator socs D Petrisko, F Gilani, M Wyse, DC Jung, S Davidson, P Gao, C Zhao, ... IEEE Micro 40 (4), 93-102, 2020 | 81 | 2020 |
Celerity: An open source RISC-V tiered accelerator fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 34 | 2017 |
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020 | 28 | 2020 |
A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 27 | 2019 |
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 25 | 2019 |
A 7.3 m output non-zeros/j sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... 2019 Symposium on VLSI Technology, C150-C151, 2019 | 21 | 2019 |
Ruche Networks: Wire-Maximal, No-Fuss NoCs: Special Session Paper DC Jung, S Davidson, C Zhao, D Richmond, MB Taylor 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2020 | 15 | 2020 |
Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ... 1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 14 | 2017 |
NoC Symbiosis (Special Session Paper) D Petrisko, C Zhao, S Davidson, P Gao, D Richmond, MB Taylor 2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2020 | 13 | 2020 |
A Fully-Synthesizable Fast-Response Digital LDO using Automatic Offset Control and Reuse C Liu, C Zhao, CJR Shi 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 3 | 2021 |