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Rob A. Rutenbar
Rob A. Rutenbar
Professor of Computer Science and Electrical and Computer Engineering, University of Pittsburgh
Verified email at pitt.edu - Homepage
Title
Cited by
Cited by
Year
Simulated annealing algorithms: An overview
RA Rutenbar
IEEE Circuits and Devices magazine 5 (1), 19-26, 1989
8761989
Computer-aided design of analog and mixed-signal integrated circuits
GGE Gielen, RA Rutenbar
Proceedings of the IEEE 88 (12), 1825-1854, 2000
7372000
OASYS: A framework for analog circuit synthesis
R Harjani, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1989
5611989
Synthesis of high-performance analog circuits in ASTRX/OBLX
ES Ochotta, RA Rutenbar, LR Carley
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996
4751996
Introduction
JM Cohn, DJ Garrod, RA Rutenbar, LR Carley
Analog Device-Level Layout Automation, 1-18, 1994
378*1994
KOAN/ANAGRAM II: New tools for device-level analog placement and routing
JM Cohn, DJ Garrod, RA Rutenbar, LR Carley
IEEE Journal of Solid-State Circuits 26 (3), 330-342, 1991
3591991
Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search
R Phelps, M Krasnicki, RA Rutenbar, LR Carley, JR Hellums
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
3472000
Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis
BR Stanisic, NK Verghese, RA Rutenbar, LR Carley, DJ Allstot
IEEE Journal of Solid-State Circuits 29 (3), 226-238, 1994
3311994
Hierarchical modeling, optimization, and synthesis for system-level analog and RF designs
RA Rutenbar, GGE Gielen, J Roychowdhury
Proceedings of the IEEE 95 (3), 640-669, 2007
2722007
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
BH Calhoun, Y Cao, X Li, K Mai, LT Pileggi, RA Rutenbar, KL Shepard
Proceedings of the IEEE 96 (2), 343-365, 2008
2502008
Reducing power by optimizing the necessary precision/range of floating-point arithmetic
JYF Tong, D Nagle, RA Rutenbar
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (3), 273-286, 2000
2322000
MAELSTROM: Efficient simulation-based synthesis for custom analog cells
M Krasnicki, R Phelps, RA Rutenbar, LR Carley
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 945-950, 1999
2071999
FPGA routing and routability estimation via Boolean satisfiability
RG Wood, RA Rutenbar
Proceedings of the 1997 ACM fifth international symposium on Field …, 1997
2021997
Placement by simulated annealing on a multiprocessor
SA Kravitz, RA Rutenbar
IEEE transactions on computer-aided design of integrated circuits and …, 1987
1971987
Why quasi-Monte Carlo is better than Monte Carlo or Latin hypercube sampling for statistical circuit analysis
A Singhee, RA Rutenbar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
1942010
A comparative study of two Boolean formulations of FPGA detailed routing constraints
GJ Nam, F Aloul, K Sakallah, R Rutenbar
Proceedings of the 2001 international symposium on Physical design, 222-227, 2001
1882001
Statistical blockade: Very fast statistical simulation and modeling of rare circuit events and its application to memory design
A Singhee, RA Rutenbar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
1772009
Analog device-level layout automation
JM Cohn, DJ Garrod, R Carley, RA Rutenbar
Springer Science & Business Media, 1994
1751994
Remembrance of circuits past: Macromodeling by data mining in large analog design spaces
H Liu, A Singhee, RA Rutenbar, LR Carley
Proceedings of the 39th annual Design Automation Conference, 437-442, 2002
1572002
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application
A Singhee, RA Rutenbar
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
1482007
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