| Development of through silicon via (TSV) interposer technology for large die (21× 21mm) fine-pitch Cu/low-k FCBGA package X Zhang, TC Chai, JH Lau, CS Selvanayagam, K Biswas, S Liu, D Pinjala, ... 2009 59th Electronic components and technology conference, 305-312, 2009 | 134 | 2009 |
| Fin shape influence on analog and RF performance of junctionless accumulation-mode bulk FinFETs K Biswas, A Sarkar, CK Sarkar Microsystem Technologies 24, 2317-2324, 2018 | 38 | 2018 |
| Spacer engineering for performance enhancement of junctionless accumulation‐mode bulk FinFETs K Biswas, A Sarkar, CK Sarkar IET Circuits, Devices & Systems 11 (1), 80-88, 2017 | 32 | 2017 |
| Impact of barrier thickness on analog, RF and linearity performance of nanoscale DG heterostructure MOSFET K Biswas, A Sarkar, CK Sarkar Superlattices and Microstructures 86, 95-104, 2015 | 32 | 2015 |
| A review of energy harvesting technology and its potential applications I Sil, S Mukherjee, K Biswas ENVIRONMENTAL AND EARTH SCIENCES RESEARCH JOURNAL 4 (2), 33-38, 2017 | 31 | 2017 |
| Impact of Fin width scaling on RF/Analog performance of junctionless accumulation-mode bulk FinFET K Biswas, A Sarkar, CK Sarkar ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 1-12, 2016 | 20 | 2016 |
| Design and optimization of bump structures of large die fine pitch copper/low-k FCBGA and copper post interconnections K Biswas, S Liu, X Zhang, TC Chai 2008 10th Electronics Packaging Technology Conference, 429-434, 2008 | 17 | 2008 |
| A review on machine learning approaches for predicting the effect of device parameters on performance of nanoscale MOSFETs R Ghoshhajra, K Biswas, A Sarkar 2021 Devices for Integrated Circuit (DevIC), 489-493, 2021 | 13 | 2021 |
| A comparative study of fiber Bragg grating based tilt sensors S Saha, K Biswas Rev. Comput. Eng. Stud. 4 (1), 41-46, 2017 | 13 | 2017 |
| Effect of varying Indium concentration of InGaAs channel on device and circuit performance of nanoscale double gate heterostructure MOSFET K Biswas, A Sarkar, CK Sarkar Micro & Nano Letters 13 (5), 690-694, 2018 | 8 | 2018 |
| Effects of detailed substrate modeling and solder layout design on the 1st and 2nd level solder joint reliability for the large die FCBGA K Biswas, S Liu, X Zhang, TC Chai EuroSimE 2008-International Conference on Thermal, Mechanical and Multi …, 2008 | 7 | 2008 |
| The 1stLevel & 2ndLevel Solder Joint Reliability Co-design for Larger Die Flip Chip Package K Biswas, S Liu, X Zhang, TC Chai 2007 9th Electronics Packaging Technology Conference, 32-36, 2007 | 7 | 2007 |
| Assessment of Dielectrics and Channel Doping Impact in Nanoscale Double Gate III–V MOSFET with Heavily Doped Source/Drain Region CKS K Biswas, A Sarkar Materials Focus 6 (2), 116-120, 2017 | 6 | 2017 |
| Device performance prediction of nanoscale junctionless FinFET using MISO artificial neural network R Ghoshhajra, K Biswas, A Sarkar Silicon 14 (13), 8141-8150, 2022 | 5 | 2022 |
| Linearity and analog performance analysis of silicon junctionless bulk FinFET considering gate electrode workfunction variability and different fin aspect ratio K Biswas, A Sarkar, CK Sarkar Silicon, 1-10, 2022 | 5 | 2022 |
| Investigation of design parameters in mems based piezoelectric vibration energy harvester I Sil, K Biswas 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 64-69, 2018 | 5 | 2018 |
| Optimizing Fin aspect ratio of junctionless bulk FinFET for application in Analog/RF circuit K Biswas, CK Sarkar 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 591-595, 2018 | 5 | 2018 |
| Structural design and optimization of MEMS based capacitive accelerometer K Sanyal, K Biswas 2017 Devices for Integrated Circuit (DevIC), 294-298, 2017 | 5 | 2017 |
| Development of numerical modeling approach on substrate warpage prediction K Biswas, S Liu, X Zhang, TC Chai 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 462-466, 2012 | 5 | 2012 |
| Structural design for Cu/low-K larger die flip chip package K Biswas, S Liu, X Zhang, TC Chai, SC Chong 2006 8th Electronics Packaging Technology Conference, 237-242, 2006 | 5 | 2006 |
Angsuman SarkarProfessor, Electronics & Communication Engg. Department, Kalyani Govt. Engg. CollegeVahvistettu sähköpostiosoite verkkotunnuksessa ieee.org
