Seuraa
Gengjie Chen
Gengjie Chen
Huawei
Vahvistettu sähköpostiosoite verkkotunnuksessa huawei.com - Kotisivu
Nimike
Viittaukset
Viittaukset
Vuosi
Clock-aware ultrascale FPGA placement with machine learning routability prediction
CW Pui, G Chen, Y Ma, EFY Young, B Yu
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 929-936, 2017
702017
RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs
CW Pui, G Chen, WK Chow, KC Lam, J Kuang, P Tu, H Zhang, ...
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
672016
Dr. CU 2.0: A scalable detailed routing framework with correct-by-construction design rule satisfaction
H Li, G Chen, B Jiang, J Chen, EFY Young
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-7, 2019
622019
RippleFPGA: Routability-driven simultaneous packing and placement for modern FPGAs
G Chen, CW Pui, WK Chow, KC Lam, J Kuang, EFY Young, B Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
572017
Salt: provably good routing topology by a novel steiner shallow-light tree algorithm
G Chen, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
492019
Dr. CU: Detailed routing by sparse grid graph and minimum-area-captured path search
G Chen, CW Pui, H Li, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
452019
Detailed routing by sparse grid graph and minimum-area-captured path search
G Chen, CW Pui, H Li, J Chen, B Jiang, EFY Young
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
382019
Routability-driven and fence-aware legalization for mixed-cell-height circuits
H Li, WK Chow, G Chen, EFY Young, B Yu
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
342018
Rest: Constructing rectilinear steiner minimum tree via reinforcement learning
J Liu, G Chen, EFY Young
2021 58th ACM/IEEE Design Automation Conference (DAC), 1135-1140, 2021
282021
Reproducible evaluation of pan-tilt-zoom tracking
G Chen, PL St-Charles, W Bouachir, GA Bilodeau, R Bergevin
2015 IEEE International Conference on Image Processing (ICIP), 2055-2059, 2015
282015
Pin-accessible legalization for mixed-cell-height circuits
H Li, WK Chow, G Chen, B Yu, EFY Young
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
202021
MARCH: Maze routing under a concurrent and hierarchical scheme for buses
J Chen, J Liu, G Chen, D Zheng, EFY Young
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
192019
AMF-placer: High-performance analytical mixed-size placer for FPGA
T Liang, G Chen, J Zhao, S Sinha, W Zhang
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
172021
Minimizing thermal gradient and pumping power in 3D IC liquid cooling network design
G Chen, J Kuang, Z Zeng, H Zhang, EFY Young, B Yu
Proceedings of the 54th annual design automation conference 2017, 1-6, 2017
172017
Fit: Fill insertion considering timing
B Jiang, X Zhang, R Chen, G Chen, P Tu, W Li, EFY Young, B Yu
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
152019
Placement for wafer-scale deep learning accelerator
B Li, Q Du, D Liu, J Zhang, G Chen, H You
Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021
82021
TreeNet: Deep point cloud embedding for routing tree construction
W Li, Y Qu, G Chen, Y Ma, B Yu
Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021
62021
A two-step search engine for large scale boolean matching under NP3 equivalence
CW Pui, P Tu, H Li, G Chen, EFY Young
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 592-598, 2018
62018
AMF-Placer 2.0: Open source timing-driven analytical mixed-size placer for large-scale heterogeneous FPGA
T Liang, G Chen, J Zhao, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
52024
Dim Sum: Light Clock Tree by Small Diameter Sum
G Chen, EFY Young
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 174-179, 2019
52019
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