| A Built-In Self-Test and In Situ Analog Circuit Optimization Platform S Lee, C Shi, J Wang, A Sanabria, H Osman, J Hu, E Sánchez-Sinencio IEEE Transactions on Circuits and Systems I: Regular Papers 65 (10), 3445-3458, 2018 | 40 | 2018 |
| Current reference circuits: A tutorial S Lee, E Sánchez-Sinencio IEEE Transactions on Circuits and Systems II: Express Briefs 68 (3), 830-836, 2021 | 29 | 2021 |
| A 1-nA 4.5-nW 289-ppm/° C Current Reference Using Automatic Calibration S Lee, S Heinrich-Barna, K Noh, K Kunz, E Sánchez-Sinencio IEEE Journal of Solid-State Circuits 55 (9), 2498-2512, 2020 | 22 | 2020 |
| Integrating metal-oxide-decorated CNT networks with a CMOS readout in a gas sensor H Lee, S Lee, DH Kim, D Perello, YJ Park, SH Hong, M Yun, S Kim Sensors 12 (3), 2582-2597, 2012 | 19 | 2012 |
| Low-voltage bandgap reference with output-regulated current mirror in 90 nm CMOS S Lee, H Lee, JK Woo, S Kim Electronics letters 46 (14), 976-977, 2010 | 17 | 2010 |
| Schmitt trigger-based key provisioning for locking analog/rf integrated circuits A Sanabria-Borbon, NG Jayasankaran, S Lee, E Sánchez-Sinencio, J Hu, ... 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 8 | 2020 |
| A time-domain digital-intensive built-in tester for analog circuits C Shi, S Lee, SS Aguilar, E Sánchez-Sinencio Journal of Electronic Testing 34, 313-320, 2018 | 5 | 2018 |
