Luis Entrena
Citado por
Citado por
Autonomous fault emulation: A new FPGA-based acceleration system for hardness evaluation
C Lopez-Ongil, M Garcia-Valderas, M Portela-Garcia, L Entrena
IEEE Transactions on Nuclear Science 54 (1), 252-261, 2007
Combinational and sequential logic optimization by redundancy addition and removal
LA Entrena, KT Cheng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1995
Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection
L Entrena, M Garcia-Valderas, R Fernandez-Cardenal, A Lindoso, ...
IEEE Transactions on Computers 61 (3), 313-322, 2010
Multi-level logic optimization by redundancy addition and removal
KT Cheng, LA Entrena
1993 European Conference on Design Automation with the European Event in …, 1993
Sequential logic optimization by redundancy addition and removal
L Entrena, KT Cheng
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993
New techniques for speeding-up fault-injection campaigns
L Berrojo, I González, F Corno, MS Reorda, G Squillero, L Entrena, ...
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
Using benchmarks for radiation testing of microprocessors and FPGAs
H Quinn, WH Robinson, P Rech, M Aguirre, A Barnard, M Desogus, ...
IEEE Transactions on Nuclear Science 62 (6), 2547-2554, 2015
AKARI-X: A pseudo random number generator for secure lightweight systems
H Martin, E San Millan, L Entrena, PPC Lopez
IOLTS, 13-15, 2011
Partial TMR in FPGAs using approximate logic circuits
AJ Sánchez-Clemente, L Entrena, M García-Valderas
IEEE Transactions on Nuclear Science 63 (4), 2233-2240, 2016
Analyzing the impact of single-event-induced charge sharing in complex circuits
S Pagliarini, F Kastensmidt, L Entrena, A Lindoso, E San Millan
IEEE Transactions on Nuclear Science 58 (6), 2768-2775, 2011
A unified environment for fault injection at any design level based on emulation
C Lopez-Ongil, L Entrena, M Garcia-Valderas, M Portela, MA Aguirre, ...
IEEE Transactions on Nuclear Science 54 (4), 946-950, 2007
An industrial environment for high-level fault-tolerant structures insertion and validation
L Berrojo, F Corno, L Entrena, I Gonzalez, C López, MS Reorda, ...
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 229-236, 2002
Fault injection in modern microprocessors using on-chip debugging infrastructures
M Portela-Garcia, C Lopez-Ongil, MGG Valderas, L Entrena
IEEE Transactions on Dependable and Secure Computing 8 (2), 308-314, 2010
High performance FPGA-based image correlation
A Lindoso, L Entrena
Journal of Real-Time Image Processing 2, 223-233, 2007
SET emulation considering electrical masking effects
L Entrena, MG Valderas, RF Cardenal, MP Garcia, CL Ongil
IEEE Transactions on Nuclear Science 56 (4), 2021-2025, 2009
Correlation-based fingerprint matching with orientation field alignment
A Lindoso, L Entrena, J Liu-Jimenez, E San Millan
Advances in Biometrics: International Conference, ICB 2007, Seoul, Korea …, 2007
A hybrid fault-tolerant LEON3 soft core processor implemented in low-end SRAM FPGA
A Lindoso, L Entrena, M García-Valderas, L Parra
IEEE Transactions on Nuclear Science 64 (1), 374-381, 2016
Error mitigation using approximate logic circuits: A comparison of probabilistic and evolutionary approaches
AJ Sanchez-Clemente, L Entrena, R Hrbacek, L Sekanina
IEEE Transactions on Reliability 65 (4), 1871-1883, 2016
Logic masking for SET mitigation using approximate logic circuits
A Sanchez-Clemente, L Entrena, M García-Valderas, C López-Ongil
2012 IEEE 18th International On-Line Testing Symposium (IOLTS), 176-181, 2012
Constrained placement methodology for reducing SER under single-event-induced charge sharing effects
L Entrena, A Lindoso, E San Millan, S Pagliarini, F Almeida, ...
IEEE Transactions on Nuclear Science 59 (4), 811-817, 2012
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