| Optimization techniques for FPGA-based wave-pipelined DSP blocks G Lakshminarayanan, B Venkataramani IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (7), 783-793, 2005 | 74 | 2005 |
| Low power wallace tree multiplier using modified full adder KB Jaiswal, N Kumar, P Seshadri, G Lakshminarayanan 2015 3rd international conference on signal processing, communication and …, 2015 | 53 | 2015 |
| A normal I/O order radix-2 FFT architecture to process twin data streams for MIMO AX Glittas, M Sellathurai, G Lakshminarayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2016 | 40 | 2016 |
| Design and analysis of novel QCA full adder-subtractor M Raj, L Gopalakrishnan, SB Ko International Journal of Electronics Letters 9 (3), 287-300, 2021 | 37 | 2021 |
| Configurable logic blocks and memory blocks for beyond-CMOS FPGA-based embedded systems M Raj, L Gopalakrishnan, SB Ko, N Naganathan, N Ramasubramanian IEEE Embedded Systems Letters 12 (4), 113-116, 2020 | 29 | 2020 |
| A novel high speed two stage detector for spectrum sensing S Geethu, GL Narayanan Procedia Technology 6, 682-689, 2012 | 26 | 2012 |
| Subtractor circuits using different wire crossing techniques in quantum-dot cellular automata M Raj, S Ahmed, L Gopalakrishnan Journal of nanophotonics 14 (2), 026007-026007, 2020 | 24 | 2020 |
| High speed generic network interface for network on chip using ping pong buffers K Swaminathan, G Lakshminarayanan, SB Ko 2012 International Symposium on Electronic System Design (ISED), 72-76, 2012 | 23 | 2012 |
| A low power 700msps 4bit time interleaved sar adc in 0.18 um cmos SG Talekar, S Ramasamy, G Lakshminarayanan, B Venkataramani TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009 | 21 | 2009 |
| Fast quantum-dot cellular automata adder/subtractor using novel fault tolerant exclusive-or gate and full adder M Raj, L Gopalakrishnan, SB Ko International Journal of Theoretical Physics 58, 3049-3064, 2019 | 19 | 2019 |
| Enhanced Noxim simulator for performance evaluation of network on chip topologies K Swaminathan, D Thakyal, SG Nambiar, G Lakshminarayanan, SB Ko 2014 Recent Advances in Engineering and Computational Sciences (RAECS), 1-5, 2014 | 19 | 2014 |
| Design and FPGA implementation of self tuned wavepipelined filters G Seetharaman, B Venkataramani, G Lakshminarayanan IETE journal of research 52 (4), 281-286, 2006 | 18 | 2006 |
| A self-adaptive mapping approach for network on chip with low power consumption A Alagarsamy, L Gopalakrishnan, S Mahilmaran, SB Ko IEEE Access 7, 84066-84081, 2019 | 17 | 2019 |
| Dynamic partial reconfigurable FFT for OFDM based communication systems C Vennila, G Lakshminarayanan, SB Ko Circuits, Systems, and Signal Processing 31, 1049-1066, 2012 | 17 | 2012 |
| Design and FPGA implementation of image block encoders with 2D-DWT G Lakshminarayanan, B Venkataramani, JS Kumar, AK Yousuf, G Sriram TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region 3 …, 2003 | 17 | 2003 |
| A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition AX Glittas, L Gopalakrishnan Integration 76, 69-75, 2021 | 16 | 2021 |
| A review of engineering techniques to suppress ambipolarity in tunnel FET KR Pasupathy, TS Manivannan, G Lakshminarayanan Silicon 14 (5), 1887-1894, 2021 | 15 | 2021 |
| Functional verification closure using optimal test scenarios for digital designs AT Vanaraj, M Raj, L Gopalakrishnan 2020 Third International Conference on Smart Systems and Inventive …, 2020 | 15 | 2020 |
| KBMA: A knowledge‐based multi‐objective application mapping approach for 3D NoC A Alagarsamy, L Gopalakrishnan, SB Ko IET Computers & Digital Techniques 13 (4), 324-334, 2019 | 15 | 2019 |
| Design of area and power efficient digital FIR filter using modified MAC unit VN Kumar, KR Nalluri, G Lakshminarayanan 2015 2nd International Conference on Electronics and Communication Systems …, 2015 | 15 | 2015 |
Seokbum KoProfessor, Dept. of ECE, Univ. of Saskatchewan; IEEE CASS Distinguished Lecturer (2024-2025)Verified email at usask.ca
