| A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2015 | 90 | 2015 |
| A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015 | 77 | 2015 |
| A 2.0–5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 51 (8), 1771-1784, 2016 | 73 | 2016 |
| A reference-less clock and data recovery circuit using phase-rotating phase-locked loop G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of solid-state circuits 49 (4), 1036-1047, 2014 | 64 | 2014 |
| A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH Modulator Dissipating 16 mW Power R Zanbaghi, S Saxena, GC Temes, TS Fiez IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1614-1625, 2012 | 54 | 2012 |
| 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
| 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 47 | 2014 |
| A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer SZ Asl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2011 | 46 | 2011 |
| Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (6), 1806-1817, 2018 | 40 | 2018 |
| A 5 Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis S Saxena, RK Nandwana, PK Hanumolu IEEE Journal of Solid-State Circuits 49 (8), 1827-1836, 2014 | 37 | 2014 |
| A 12.5-bit 4 MHz 13.8 mW MASH Modulator With Multirated VCO-Based ADC S Zaliasl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1604-1613, 2012 | 37 | 2012 |
| A 7 Gb/s embedded clock transceiver for energy proportional links T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, 2015 | 27 | 2015 |
| A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2017 | 21 | 2017 |
| 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 17 | 2015 |
| A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 16 | 2014 |
| An energy-efficient 3Gb/s PAM4 full-duplex transmitter with 2-tap feed forward equalizer S Mukherjee, A Das, S Seth, S Saxena IEEE Transactions on Circuits and Systems II: Express Briefs 67 (5), 916-920, 2020 | 15 | 2020 |
| 23.1 a 16mb/s-to-8gb/s 14.1-to-5.9 pj/b source synchronous transceiver using dvfs and rapid on/off in 65nm cmos G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2016 | 15 | 2016 |
| A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353, 2015 | 15 | 2015 |
| 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 492-493, 2017 | 12 | 2017 |
| A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC RK Nandwana, S Saxena, A Elshazly, K Mayaram, PK Hanumolu IEEE Transactions on Circuits and Systems I: Regular Papers 64 (2), 283-295, 2016 | 12 | 2016 |
Romesh NandwanaTechnical Leader, Cisco SystemsVerified email at illinois.edu
