| Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction M Koskela, K Immonen, M Mäkitalo, A Foi, T Viitanen, P Jääskeläinen, ... ACM Transactions on Graphics (TOG) 38 (5), 1-14, 2019 | 63 | 2019 |
| HW/SW Co-design Toolset for Customization of Exposed Datapath Processors P Jääskeläinen, T Viitanen, J Takala, H Berg Computing Platforms for Software-Defined Radio, 147-164, 2017 | 61 | 2017 |
| Code density and energy efficiency of exposed datapath architectures P Jääskeläinen, H Kultala, T Viitanen, J Takala Journal of Signal Processing Systems 80, 49-64, 2015 | 33 | 2015 |
| Foveated Real-Time Path Tracing in Visual-Polar Space M Koskela, A Lotvonen, M Mäkitalo, P Kivi, T Viitanen, P Jääskeläinen Proceedings of 30th Eurographics Symposium on Rendering, 2019 | 31 | 2019 |
| Transport-Triggered Soft Cores P Jääskeläinen, A Tervo, GP Vayá, T Viitanen, N Behmann, J Takala, ... 2018 IEEE International Parallel and Distributed Processing Symposium …, 2018 | 29 | 2018 |
| Are we done with ray tracing? A Keller, T Viitanen, C Barré-Brisebois, C Schied, M McGuire SIGGRAPH Courses, 3:1-3:381, 2019 | 28 | 2019 |
| An integrated hardware/software design methodology for signal processing systems L Li, C Sau, T Fanni, J Li, T Viitanen, F Christophe, F Palumbo, L Raffo, ... Journal of Systems Architecture 93, 1-19, 2019 | 27 | 2019 |
| Foveated path tracing: a literature review and a performance gain analysis M Koskela, T Viitanen, P Jääskeläinen, J Takala Advances in Visual Computing: 12th International Symposium, ISVC 2016, Las …, 2016 | 21 | 2016 |
| Simplified Floating-Point Division and Square Root T Viitanen, P Jääskeläinen, O Esko, J Takala IEEE International Conference on Acoustics, Speech and Signal Processing …, 2013 | 20 | 2013 |
| PLOCTree: A Fast, High-Quality Hardware BVH Builder T Viitanen, M Koskela, P Jääskeläinen, A Tervo, J Takala Proceedings of the ACM on Computer Graphics and Interactive Techniques 1 (2 …, 2018 | 19 | 2018 |
| MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing T Viitanen, M Koskela, P Jääskeläinen, H Kultala, J Takala ACM Transactions on Graphics (TOG) 36 (5), 169, 2017 | 16 | 2017 |
| Sparse Sampling for Real-time Ray Tracing. T Viitanen, M Koskela, K Immonen, M Mäkitalo, P Jääskeläinen, J Takala VISIGRAPP (1: GRAPP), 295-302, 2018 | 15 | 2018 |
| Heuristics for greedy transport triggered architecture interconnect exploration T Viitanen, H Kultala, P Jääskeläinen, J Takala 2014 International Conference on Compilers, Architectures and Synthesis for …, 2014 | 15 | 2014 |
| LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor H Kultala, T Viitanen, H Berg, P Jääskeläinen, J Multanen, M Kokkonen, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (5 …, 2019 | 14 | 2019 |
| Variable length instruction compression on transport triggered architectures J Helkala, T Viitanen, H Kultala, P Jääskeläinen, J Takala, T Zetterman, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 12 | 2014 |
| AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition J IJzerman, T Viitanen, P Jääskeläinen, H Kultala, L Lehtonen, M Peemen, ... Proceedings of the 18th International Conference on Embedded Computer …, 2018 | 11 | 2018 |
| Hardware design methodology using lightweight dataflow and its integration with low power techniques T Fanni, L Li, T Viitanen, C Sau, R Xie, F Palumbo, L Raffo, H Huttunen, ... Journal of Systems Architecture 78, 15-29, 2017 | 11 | 2017 |
| Multi bounding volume hierarchies for ray tracing pipelines T Viitanen, M Koskela, P Jääskeläinen, J Takala SIGGRAPH ASIA 2016 Technical Briefs, 1-4, 2016 | 11 | 2016 |
| Instantaneous foveated preview for progressive Monte Carlo rendering MK Koskela, KV Immonen, TT Viitanen, PO Jääskeläinen, JI Multanen, ... Computational Visual Media 4, 267-276, 2018 | 10 | 2018 |
| Lotta: Energy-efficient processor for always-on applications J Multanen, H Kultala, P Jääskeläinen, T Viitanen, A Tervo, J Takala 2018 IEEE International Workshop on Signal Processing Systems (SiPS), 193-198, 2018 | 9 | 2018 |
Jarmo TakalaTampere UniversityVerified email at tuni.fi
