| A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC A Elkholy, T Anand, WS Choi, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (4), 867-881, 2015 | 136 | 2015 |
| Cheetah: Optimizing and accelerating homomorphic encryption for private inference B Reagen*, WS Choi*, Y Ko, VT Lee, HHS Lee, GY Wei, D Brooks 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 93 | 2021 |
| A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, 2015 | 81 | 2015 |
| A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, 2015 | 75 | 2015 |
| A reference-less clock and data recovery circuit using phase-rotating phase-locked loop G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of solid-state circuits 49 (4), 1036-1047, 2014 | 64 | 2014 |
| A 10-MHz 2–800-mA 0.5–1.5-V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes SJ Kim, WS Choi, R Pilawa-Podgurski, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (3), 814-824, 2017 | 53 | 2017 |
| A 10-MHz 2–800-mA 0.5–1.5-V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes SJ Kim, WS Choi, R Pilawa-Podgurski, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (3), 814-824, 2017 | 53 | 2017 |
| 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 43 | 2014 |
| 3.8 A 0.45-to-0.7 V 1-to-6Gb/S 0.29-to-0.58 pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS WS Choi, G Shu, M Talegaonkar, Y Liu, D Wei, L Benini, PK Hanumolu 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 37 | 2015 |
| A burst-mode digital receiver with programmable input jitter filtering for energy proportional links WS Choi, T Anand, G Shu, A Elshazly, PK Hanumolu IEEE Journal of Solid-State Circuits 50 (3), 737-748, 2015 | 29 | 2015 |
| Guaranteeing local differential privacy on ultra-low-power systems WS Choi, M Tomei, JRS Vicarte, PK Hanumolu, R Kumar 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 28 | 2018 |
| A 2.8 mW/Gb/s, 14 Gb/s serial link transceiver S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2017 | 18 | 2017 |
| 250 Mbps–5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13m CMOS SY Lee, HR Lee, YH Kwak, WS Choi, BJ Yoo, D Shim, C Kim, DK Jeong IEEE journal of solid-state circuits 46 (11), 2560-2570, 2011 | 18 | 2011 |
| Cheetah: Optimizations and methods for privacy preserving inference via homomorphic encryption B Reagen*, W Choi*, Y Ko, V Lee, GY Wei, HHS Lee, D Brooks arXiv preprint arXiv:2006.00505 3, 2020 | 16 | 2020 |
| A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 15 | 2014 |
| A 1.6 ps peak-INL 5.3 ns range two-step digital-to-time converter in 65nm CMOS A Elmallah, MG Ahmed, A Elkholy, WS Choi, PK Hanumolu 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018 | 13 | 2018 |
| A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353, 2015 | 13 | 2015 |
| A 15Gb/s 1.9 pJ/bit sub-baud-rate digital CDR D Kim, WS Choi, A Elkholy, J Kenney, PK Hanumolu 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018 | 11 | 2018 |
| A 0.45–0.7 V 1–6 Gb/s 0.29–0.58 pJ/b source-synchronous transceiver using near-threshold operation WS Choi, G Shu, M Talegaonkar, Y Liu, D Wei, L Benini, PK Hanumolu IEEE Journal of Solid-State Circuits 53 (3), 884-895, 2018 | 11 | 2018 |
| 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 492-493, 2017 | 11 | 2017 |
Ahmed ElkholyUniversity of IllinoisVerified email at illinois.edu
