Jun Lin
Jun Lin
Verified email at nju.edu.cn
Title
Cited by
Cited by
Year
Efficient decoder design for nonbinary quasicyclic LDPC codes
J Lin, J Sha, Z Wang, L Li
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (5), 1071-1082, 2010
812010
An Efficient List Decoder Architecture for Polar Codes
J Lin, Z Yan
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2015
792015
Flexible LDPC decoder design for multigigabit-per-second applications
C Zhang, Z Wang, J Sha, L Li, J Lin
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (1), 116-124, 2009
652009
Symbol-decision successive cancellation list decoder for polar codes
C Xiong, J Lin, Z Yan
IEEE Transactions on Signal Processing 64 (3), 675-687, 2015
592015
A High Throughput List Decoder Architecture for Polar Codes
J Lin, C Xiong, Z Yan
IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24 (6), 2378-2391, 2016
512016
An efficient VLSI architecture for nonbinary LDPC decoders
J Lin, J Sha, Z Wang, L Li
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (1), 51-55, 2010
502010
Efficient hardware architectures for deep convolutional neural network
J Wang, J Lin, Z Wang
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1941-1953, 2017
442017
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach
Z Wang, J Lin, Z Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
442017
Efficient shuffle network architecture and application for WiMAX LDPC decoders
J Lin, Z Wang, L Li, J Sha, M Gao
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (3), 215-219, 2009
422009
An energy-efficient architecture for binary weight convolutional neural networks
Y Wang, J Lin, Z Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (2), 280-293, 2017
412017
A reduced latency list decoding algorithm for polar codes
J Lin, C Xiong, Z Yan
Signal Processing Systems (SiPS), 2014 IEEE Workshop on, 0
41*
A multimode area-efficient SCL polar decoder
C Xiong, J Lin, Z Yan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (12 …, 2016
292016
Efficient shuffled decoder architecture for nonbinary quasi-cyclic LDPC codes
J Lin, Z Yan
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 21 (9 …, 2013
272013
Efficient convolution architectures for convolutional neural network
J Wang, J Lin, Z Wang
2016 8th International Conference on Wireless Communications & Signal …, 2016
232016
Symbol-based successive cancellation list decoder for polar codes
C Xiong, J Lin, Z Yan
Signal Processing Systems (SiPS), 2014 IEEE Workshop on, 0
22*
An efficient fully parallel decoder architecture for nonbinary LDPC codes
J Lin, Z Yan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (12 …, 2013
202013
Reduced complexity belief propagation decoders for polar codes
J Lin, C Xiong, Z Yan
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
192015
Decoder design for RS-based LDPC codes
J Sha, J Lin, Z Wang, L Li, M Gao
IEEE Transactions on Circuits and Systems II: Express Briefs 56 (9), 724-728, 2009
192009
Low complexity message passing detection algorithm for large-scale MIMO systems
J Zeng, J Lin, Z Wang
IEEE Wireless Communications Letters 7 (5), 708-711, 2018
182018
A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning
M Wang, S Lu, D Zhu, J Lin, Z Wang
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 223-226, 2018
172018
The system can't perform the operation now. Try again later.
Articles 1–20