Mengwei Si
Steep-slope hysteresis-free negative capacitance MoS2 transistors
M Si, CJ Su, C Jiang, NJ Conrad, H Zhou, KD Maize, G Qiu, CT Wu, ...
Nature Nanotechnology 13 (1), 24-28, 2017
Switching mechanism in single-layer molybdenum disulfide transistors: an insight into current flow across Schottky barriers
H Liu, M Si, Y Deng, AT Neal, Y Du, S Najmaei, PM Ajayan, J Lou, PD Ye
ACS Nano 8 (1), 1031-1038, 2014
Molecular Doping of Multilayer MoS₂ Field-Effect Transistors: Reduction in Sheet and Contact Resistances
Y Du, H Liu, AT Neal, M Si, PD Ye
IEEE Electron Device Letters 34 (10), 1328 - 1330, 2013
Statistical Study of Deep Sub-Micron Dual-Gated Field-Effect Transistors on Monolayer CVD Molybdenum Disulfide Films
H Liu, M Si, S Najmaei, AT Neal, Y Du, PM Ajayan, J Lou, PD Ye
Nano Letters 13 (6), 2640-2646, 2013
High-Performance Depletion/Enhancement-ode -Ga2O3 on Insulator (GOOI) Field-Effect Transistors With Record Drain Currents of 600/450 mA/mm
H Zhou, M Si, S Alghamdi, G Qiu, L Yang, DY Peide
IEEE Electron Device Letters 38 (1), 103-106, 2016
One-dimensional van der Waals material tellurium: Raman spectroscopy under strain and magneto-transport
Y Du, G Qiu, Y Wang, M Si, X Xu, W Wu, PD Ye
Nano letters 17 (6), 3965-3973, 2017
The Effect of Dielectric Capping on Few-Layer Phosphorene Transistors: Tuning the Schottky Barrier Heights
H Liu, AT Neal, M Si, Y Du, PD Ye
IEEE Electron Device Letters 35 (7), 795 - 797, 2014
Ferroelectric Field-Effect Transistors Based on MoS2 and CuInP2S6 Two-Dimensional Van der Waals Heterostructure
M Si, PY Liao, G Qiu, Y Duan, PD Ye
ACS nano 12 (7), 6700–6705, 2018
A ferroelectric semiconductor field-effect transistor
M Si, AK Saha, S Gao, G Qiu, J Qin, Y Duan, J Jian, C Niu, H Wang, W Wu, ...
Nature Electronics 2 (12), 580-586, 2019
A critical review of recent progress on negative capacitance field-effect transistors
MA Alam, M Si, PD Ye
Applied Physics Letters 114 (9), 090401, 2019
Al2O3/ -Ga2O3(-201) Interface Improvement Through Piranha Pretreatment and Postdeposition Annealing
H Zhou, S Alghmadi, M Si, G Qiu, DY Peide
IEEE Electron Device Letters 37 (11), 1411-1414, 2016
Performance Potential and Limit of MoS2 Transistors
X Li, L Yang, M Si, S Li, M Huang, P Ye, Y Wu
Advanced Materials 27 (9), 1547-1552, 2015
Steep-Slope WSe2 Negative Capacitance Field-Effect Transistor
M Si, C Jiang, W Chung, Y Du, MA Alam, PD Ye
Nano letters 18 (8), 3682–3687, 2018
Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs
SH Shin, MA Wahab, M Masuduzzaman, K Maize, J Gu, M Si, A Shakouri, ...
IEEE Transactions on Electron Devices 62 (11), 3516-3523, 2015
Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec
W Chung, M Si, DY Peide
2017 IEEE International Electron Devices Meeting (IEDM), 15.3. 1-15.3. 4, 2017
First demonstration of Ge nanowire CMOS circuits: Lowest SS of 64 mV/dec, highest gmax of 1057 μS/μm in Ge nFETs and highest maximum voltage gain of 54 V/V in Ge CMOS inverters
H Wu, W Wu, M Si, DY Peide
2015 IEEE International Electron Devices Meeting (IEDM), 2.1. 1-2.1. 4, 2015
Sub-60 mV/dec ferroelectric HZO MoS2negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance
M Si, C Jiang, CJ Su, YT Tang, L Yang, W Chung, MA Alam, PD Ye
2017 IEEE International Electron Devices Meeting (IEDM), 23.5. 1-23.5. 4, 2017
Ferroelectric Polarization Switching of Hafnium Zirconium Oxide in Ferroelectric/Dielectric Stack
M Si, X Lyu, PD Ye
ACS Appl. Electron. Mater. 1 (5), 745-751, 2019
High-performance InAlN/GaN MOSHEMTs enabled by atomic layer epitaxy MgCaO as gate dielectric
H Zhou, X Lou, NJ Conrad, M Si, H Wu, S Alghamdi, S Guo, RG Gordon, ...
IEEE Electron Device Letters 37 (5), 556-559, 2016
First experimental demonstration of Ge 3D FinFET CMOS circuits
H Wu, W Luo, H Zhou, M Si, J Zhang, DY Peide
2015 Symposium on VLSI Technology (VLSI Technology), T58-T59, 2015
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Artikkelit 1–20